Канал: Maharshi Sanand Yadav T

What is Propagation Delay || #verilog || #ece || #vlsi || #vlsitraining

What is Propagation Delay || #verilog || #ece || #vlsi || #vlsitraining

Level Shifter #ece #tmsytutorials

Level Shifter #ece #tmsytutorials

#1 || Number of Directories || bash scripting || #bashscripting

#1 || Number of Directories || bash scripting || #bashscripting

parameters of .lib || cell rise, cell fall, rise transition, fall transition || .lib || #STA || #ece

parameters of .lib || cell rise, cell fall, rise transition, fall transition || .lib || #STA || #ece

What is Rise Time (Tr), Fall Time (Tf) and Delay Time (Td)

What is Rise Time (Tr), Fall Time (Tf) and Delay Time (Td)

Experiment: 8.a || CMOS NAND GATE || Schematic | Layout | DSCH 3.1 | Microwind

Experiment: 8.a || CMOS NAND GATE || Schematic | Layout | DSCH 3.1 | Microwind

1- bit Comparator || Gate Level Modelling || #vlsi #vlsidesign #tmsy

1- bit Comparator || Gate Level Modelling || #vlsi #vlsidesign #tmsy

CMOS Inverter Schematic & Layout || Microwind 3.1 || #DICD_LAB || #ECE2020-2024 || 6th SEM || #ece

CMOS Inverter Schematic & Layout || Microwind 3.1 || #DICD_LAB || #ECE2020-2024 || 6th SEM || #ece

Write structural Verilog HDL models for 4-bit binary adder and subtractor || #verilog

Write structural Verilog HDL models for 4-bit binary adder and subtractor || #verilog

Experiment 1.b || 4-bit adder and subtractor || Verilog Code, Working Explanation || #verilog

Experiment 1.b || 4-bit adder and subtractor || Verilog Code, Working Explanation || #verilog

3T DRAM || PC414EC || 3 Transistor Dynamic Random Access Memory || #vlsidesign

3T DRAM || PC414EC || 3 Transistor Dynamic Random Access Memory || #vlsidesign

1T DRAM || PC414ECE || 1 Transistor Dynamic Random Access Memory

1T DRAM || PC414ECE || 1 Transistor Dynamic Random Access Memory

2-bit up counter design and implementation using SR-FF || synchronous || positive-edge trigger

2-bit up counter design and implementation using SR-FF || synchronous || positive-edge trigger

verilog code of SR-FF || positive edge trigger || #tmsy

verilog code of SR-FF || positive edge trigger || #tmsy

4x4 NOR Based ROM Array || #NORBasedROMArray#4x4ROMArray#Readonlymemory#ROMCircuit #tmsy

4x4 NOR Based ROM Array || #NORBasedROMArray#4x4ROMArray#Readonlymemory#ROMCircuit #tmsy

Path Sensitization Method || #unit5 #pc702ec #vlsi #ece #osmaniauniversity #vlsidesign #engineering

Path Sensitization Method || #unit5 #pc702ec #vlsi #ece #osmaniauniversity #vlsidesign #engineering

Source Degenerated Current Mirror || #vlsi #ece #vlsidesign #pc702ec #tmsy

Source Degenerated Current Mirror || #vlsi #ece #vlsidesign #pc702ec #tmsy

NMOS Current Mirror || Output Impedance, Resistance || #tmsy #vlsi #vlsidesign #engineering #ece

NMOS Current Mirror || Output Impedance, Resistance || #tmsy #vlsi #vlsidesign #engineering #ece

Small Signal Equivalent Model for NMOS, I.e. MOSFET #ece #vlsi #vlsidesign #tmsy

Small Signal Equivalent Model for NMOS, I.e. MOSFET #ece #vlsi #vlsidesign #tmsy

What is Current Mirror || Why is Current Mirror || NMOS Current Mirror || #tmsy #vlsidesign #vlsi

What is Current Mirror || Why is Current Mirror || NMOS Current Mirror || #tmsy #vlsidesign #vlsi

Logic Gates Implementation using Multiplexer #ece #vlsi #osmaniauniversity #engineering #vlsidesign

Logic Gates Implementation using Multiplexer #ece #vlsi #osmaniauniversity #engineering #vlsidesign

Stick Diagram of CMOS NOT GATE || CMOS Inverter || #inverter #cmos #gate #tmsy #vlsi #vlsidesign

Stick Diagram of CMOS NOT GATE || CMOS Inverter || #inverter #cmos #gate #tmsy #vlsi #vlsidesign

How to Take Attendance in MCET ERP || #MCET || #TMSY #microsoft

How to Take Attendance in MCET ERP || #MCET || #TMSY #microsoft

NMOS Inverter Delay #VLSI #inverter || The Delay unit in MOS Circuits #ece #osmaniauniversity #tmsy

NMOS Inverter Delay #VLSI #inverter || The Delay unit in MOS Circuits #ece #osmaniauniversity #tmsy

Designing a Full Adder using CMOS Schematic| #DesigningFullAdder #CMOSSchematic #DigitalLogic #VLSI

Designing a Full Adder using CMOS Schematic| #DesigningFullAdder #CMOSSchematic #DigitalLogic #VLSI

Output Conductance gds || #conductance || #ece #vlsi #osmaniauniversity

Output Conductance gds || #conductance || #ece #vlsi #osmaniauniversity

Transconductance gm || #conductance || #ece #vlsi #osmaniauniversity #engineering

Transconductance gm || #conductance || #ece #vlsi #osmaniauniversity #engineering

Schematic for CMOS HALF ADDER || #schematics || #vlsi || #vlsidesign || #ece || #osmaniauniversity

Schematic for CMOS HALF ADDER || #schematics || #vlsi || #vlsidesign || #ece || #osmaniauniversity

CMOS OR SCHEMATIC || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi

CMOS OR SCHEMATIC || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi

Final Schematic of CMOS XNOR || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi

Final Schematic of CMOS XNOR || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi

CMOS XNOR Boolean Expression to draw Schematic | #schematics #madeeasy #ace #ece #vlsidesign #vlsi

CMOS XNOR Boolean Expression to draw Schematic | #schematics #madeeasy #ace #ece #vlsidesign #vlsi

CMOS XOR Boolean Expression to draw Schematic || #schematics #ace #ece #vlsidesign #vlsi

CMOS XOR Boolean Expression to draw Schematic || #schematics #ace #ece #vlsidesign #vlsi

CMOS NOR Schematic || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi

CMOS NOR Schematic || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi

24th Oct 2022 || Happy Diwali || @maharshisanandyadav

24th Oct 2022 || Happy Diwali || @maharshisanandyadav

Video Rendering Time || Ryzen 5 5600H || RTX 3050 || 8GB RAM || Camtasia || Size 3 min 20 sec😎👨‍💻

Video Rendering Time || Ryzen 5 5600H || RTX 3050 || 8GB RAM || Camtasia || Size 3 min 20 sec😎👨‍💻

CMOS NAND SCHEMATIC || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi

CMOS NAND SCHEMATIC || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi

Working of CMOS Inverter || How to draw Schematic of CMOS Inverter

Working of CMOS Inverter || How to draw Schematic of CMOS Inverter

CMOS OR LTSPICE

CMOS OR LTSPICE

CMOS AND LTSPICE

CMOS AND LTSPICE

CMOS NOR LTSPICE@maharshisanandyadav || #TMSY

CMOS NOR LTSPICE@maharshisanandyadav || #TMSY

CMOS NOT LTSPICE || @maharshisanandyadav || #TMSY

CMOS NOT LTSPICE || @maharshisanandyadav || #TMSY

CMOS NAND LTSPICE

CMOS NAND LTSPICE

2x4 CMOS Decoder in LT Spice || EDA Lab || Experiment 4 || #TMSY || @maharshisanandyadav

2x4 CMOS Decoder in LT Spice || EDA Lab || Experiment 4 || #TMSY || @maharshisanandyadav

Verilog Code for a 16:1 Multiplexer using Keyword TASK and verify its functionality using Stimulus.

Verilog Code for a 16:1 Multiplexer using Keyword TASK and verify its functionality using Stimulus.

CMOS OR 2 Switch Level Modelling

CMOS OR 2 Switch Level Modelling

Ubuntu Installation using Microsoft Store || UBUNTU 20.04.4 LTS

Ubuntu Installation using Microsoft Store || UBUNTU 20.04.4 LTS

Lord Ganesh || 2nd September 2022 || @maharshisanandyadav

Lord Ganesh || 2nd September 2022 || @maharshisanandyadav

Lord Ganesh || 31st August 2022 || @maharshisanandyadav

Lord Ganesh || 31st August 2022 || @maharshisanandyadav

How to do Parasitic Extraction PEX 2D || CMOS NAND 2 || Layout || GLADE

How to do Parasitic Extraction PEX 2D || CMOS NAND 2 || Layout || GLADE

How to do Layout vs Schematic || LVS || CMOS NAND 2 || GLADE

How to do Layout vs Schematic || LVS || CMOS NAND 2 || GLADE

Glade || CMOS_NAND_2_Layout

Glade || CMOS_NAND_2_Layout

GLADE || CMOS_NOT_1_Layout

GLADE || CMOS_NOT_1_Layout

CMOS_XOR_2 || Switch Level Modelling || EDA playground

CMOS_XOR_2 || Switch Level Modelling || EDA playground

CMOS_AND_2 || Switch Level Modelling || Verilog

CMOS_AND_2 || Switch Level Modelling || Verilog

CMOS NOR 2 Switch Level Modelling || EDA playground

CMOS NOR 2 Switch Level Modelling || EDA playground

Kashi Ganga Aarthi

Kashi Ganga Aarthi

Kashi Ganga Aarthi || 7PM || 16th Aug 2022

Kashi Ganga Aarthi || 7PM || 16th Aug 2022

Varanasi Junction Railway Station

Varanasi Junction Railway Station

CMOS_NOT_1_Test Bench || EDA Playground || @maharshisanandyadav

CMOS_NOT_1_Test Bench || EDA Playground || @maharshisanandyadav

CMOS_NOT_1 || Switch Level Modelling

CMOS_NOT_1 || Switch Level Modelling

CMOS NAND 2 Switch Level Modelling || EDA Playground

CMOS NAND 2 Switch Level Modelling || EDA Playground

CMOS NOT 1 Switch Level Modelling || EDA Play Ground #edaplayground #verilog #ece #vlsi

CMOS NOT 1 Switch Level Modelling || EDA Play Ground #edaplayground #verilog #ece #vlsi

Full_Adder_Nexys4_DDR

Full_Adder_Nexys4_DDR

NMOS Drain and Transfer Characteristics || LTSPICE

NMOS Drain and Transfer Characteristics || LTSPICE

Unit 5 || ASIC || FULL CUSTOM || SEMI CUSTOM || PROGRAMMABLE ASIC

Unit 5 || ASIC || FULL CUSTOM || SEMI CUSTOM || PROGRAMMABLE ASIC

Write a Verilog HDL Program in Behavioral Model for 8:3 Encoder || #DSDV

Write a Verilog HDL Program in Behavioral Model for 8:3 Encoder || #DSDV

Write a Verilog HDL Program in Behavioral Model for 8:1 Multiplexer | https://www.tmsytutorials.com/

Write a Verilog HDL Program in Behavioral Model for 8:1 Multiplexer | https://www.tmsytutorials.com/

Loops || For || While || Repeat || Forever || Tasks || Functions || 3rd June 2021 || #tmsy

Loops || For || While || Repeat || Forever || Tasks || Functions || 3rd June 2021 || #tmsy

Write a Verilog HDL program for 3:8 Decoder realization through 2:4 Decoder

Write a Verilog HDL program for 3:8 Decoder realization through 2:4 Decoder

Write a Verilog HDL Program in Behavioral Modelling for 2 x 4 Decoder

Write a Verilog HDL Program in Behavioral Modelling for 2 x 4 Decoder

How to Print Xilinx Outputs || #TMSY #dsdv

How to Print Xilinx Outputs || #TMSY #dsdv

Write a Verilog HDL Program in Gate Level Modelling for Full Adder in Xilinx ISE 14.7

Write a Verilog HDL Program in Gate Level Modelling for Full Adder in Xilinx ISE 14.7

Verilog Code of Full Adder in Notepad++

Verilog Code of Full Adder in Notepad++

Full Adder using Two Half Adders and One OR gate

Full Adder using Two Half Adders and One OR gate

DCCN Lab || Addition of Two Numbers || #TMSY

DCCN Lab || Addition of Two Numbers || #TMSY

How to Install Oracle Enterprise Linux 64-bit [OEL] on VMWare Workstation & Connect via Putty

How to Install Oracle Enterprise Linux 64-bit [OEL] on VMWare Workstation & Connect via Putty

Unit-3|| Meghana - Flip Flop Conversions || CPLD || FPGA || Digital Electronics || CSE || #TMSY

Unit-3|| Meghana - Flip Flop Conversions || CPLD || FPGA || Digital Electronics || CSE || #TMSY

Sanjana Presentation on PAL || 28-01-2022 || #DE || #TMSY

Sanjana Presentation on PAL || 28-01-2022 || #DE || #TMSY

Flip Flop Conversions || De-Multiplexer || Full Adder using Two HA & One OR Gate || #DE || #TMSY

Flip Flop Conversions || De-Multiplexer || Full Adder using Two HA & One OR Gate || #DE || #TMSY

MOD 5 ASYNCHRONOUS UP-COUNTER USING JK-FF USING POSITIVE EDGE TRIGGER || #TMSY || CSE || ECE

MOD 5 ASYNCHRONOUS UP-COUNTER USING JK-FF USING POSITIVE EDGE TRIGGER || #TMSY || CSE || ECE

Master-Slave JK-FF || Mealy 00 || Quin Mcklusey f(A,B,C,D,E)=∑𝒎(𝟎,𝟏,𝟐,𝟖,𝟗,𝟏𝟓,𝟏𝟕,𝟐𝟏,𝟐𝟒,𝟐𝟓,𝟐𝟕,𝟑𝟏)

Master-Slave JK-FF || Mealy 00 || Quin Mcklusey f(A,B,C,D,E)=∑𝒎(𝟎,𝟏,𝟐,𝟖,𝟗,𝟏𝟓,𝟏𝟕,𝟐𝟏,𝟐𝟒,𝟐𝟓,𝟐𝟕,𝟑𝟏)

Verilog Code || SRFF NEGEDGE TRIGGER || Digital Electronics || #TMSY || #CSE || #ECE || #MCET

Verilog Code || SRFF NEGEDGE TRIGGER || Digital Electronics || #TMSY || #CSE || #ECE || #MCET

Verilog Code || D-FF POSEDGE TRIGGER || Digital Electronics || #TMSY || CSE || ECE

Verilog Code || D-FF POSEDGE TRIGGER || Digital Electronics || #TMSY || CSE || ECE

Unit 5 || ASM Chart || #TMSY || CSE

Unit 5 || ASM Chart || #TMSY || CSE

Verilog Code || SR-FF POSEDGE TRIGGER || #TMSY || Unit-4 || Digital Electronics || CSE

Verilog Code || SR-FF POSEDGE TRIGGER || #TMSY || Unit-4 || Digital Electronics || CSE

Unit 5 || Partition Minimization Technique || Digital Electronics || #tmsy || #12-01-2022

Unit 5 || Partition Minimization Technique || Digital Electronics || #tmsy || #12-01-2022

Unit 5 || '1010' & '0001' Mealy FSM || '101'Moore using D-FF || Digital Electronics || 11-01-2022

Unit 5 || '1010' & '0001' Mealy FSM || '101'Moore using D-FF || Digital Electronics || 11-01-2022

Unit 5 || Finite State Machines || Mealy, Moore State Diagram & State Table || Reduced State Table

Unit 5 || Finite State Machines || Mealy, Moore State Diagram & State Table || Reduced State Table

Unit 4 || #Registers || #Shift Registers || #SISO || #SIPO || #PIPO || #PISO || #TMSY

Unit 4 || #Registers || #Shift Registers || #SISO || #SIPO || #PIPO || #PISO || #TMSY

Unit 4 || Asynchronous Counters || 2-bit UP Counter, DOWN Counter, UP/DOWN Counter, Modulus Counter

Unit 4 || Asynchronous Counters || 2-bit UP Counter, DOWN Counter, UP/DOWN Counter, Modulus Counter

Unit 4 || 2-BIT SYNCHRONOUS UP-COUNTER JK-FF || 3-BIT SYNCHRONOUS UP-COUNTER JK-FF || 3-BIT UPDOWN

Unit 4 || 2-BIT SYNCHRONOUS UP-COUNTER JK-FF || 3-BIT SYNCHRONOUS UP-COUNTER JK-FF || 3-BIT UPDOWN

Unit 4 || D-Latch || SRFF || DFF || JKFF || TFF

Unit 4 || D-Latch || SRFF || DFF || JKFF || TFF

Unit 4 || Sequential Circuits || Digital Electronics || CSE A & B || 21-12-2021 || #TMSY

Unit 4 || Sequential Circuits || Digital Electronics || CSE A & B || 21-12-2021 || #TMSY

Realization of Half Subtractor using NAND gates || Digital Electronics

Realization of Half Subtractor using NAND gates || Digital Electronics

Realization of Half Subtractor using Logic Gates

Realization of Half Subtractor using Logic Gates

Realization of Half Subtractor using Basic Gates

Realization of Half Subtractor using Basic Gates

Half Subtractor

Half Subtractor

Minimize the following expression using K map and realize using NOR gate

Minimize the following expression using K map and realize using NOR gate

Implement Full Adder using 3x8 Decoder and suitable gates #osmaniauniversity #ece #vlsi #digital

Implement Full Adder using 3x8 Decoder and suitable gates #osmaniauniversity #ece #vlsi #digital

Expand the given Boolean expression to maxterms and minterms

Expand the given Boolean expression to maxterms and minterms

Convert the binary number 11011101 to Gray code

Convert the binary number 11011101 to Gray code

Full Adder

Full Adder

III SEM || CSE - B || Digital Electronics || Code Convertors || 1 bit Comparator

III SEM || CSE - B || Digital Electronics || Code Convertors || 1 bit Comparator

Realization of Half Adder using Logic Gates || Digital Electronics

Realization of Half Adder using Logic Gates || Digital Electronics

Realization of Half Adder using Basic Gates || Digital Electronics

Realization of Half Adder using Basic Gates || Digital Electronics

Working of Half Adder

Working of Half Adder

What is meant by Combinational Circuit || Digital Electronics || #TMSY

What is meant by Combinational Circuit || Digital Electronics || #TMSY

How to Dump Verilog Code || NEXYS 4 DDR || #xilinx #vlsi #fpga #ece #verilog #edaece #dsdv

How to Dump Verilog Code || NEXYS 4 DDR || #xilinx #vlsi #fpga #ece #verilog #edaece #dsdv

9. CMOS FULL ADDER || DSCH || Microwind || EDA LAB || 7th SEM || ECE || #TMSY

9. CMOS FULL ADDER || DSCH || Microwind || EDA LAB || 7th SEM || ECE || #TMSY

3. CMOS OR GATE #microwind #ece #edaece #osmaniauniversity #vlsi #engineering

3. CMOS OR GATE #microwind #ece #edaece #osmaniauniversity #vlsi #engineering

8. CMOS HALF ADDER || DSCH || Microwind || EDA LAB || 7th SEM || ECE || #TMSY

8. CMOS HALF ADDER || DSCH || Microwind || EDA LAB || 7th SEM || ECE || #TMSY

6. CMOS XOR GATE || DSCH || Microwind || EDA LAB || 7th SEM || ECE || #TMSY

6. CMOS XOR GATE || DSCH || Microwind || EDA LAB || 7th SEM || ECE || #TMSY

2. CMOS AND GATE #ece #tmsy #microwind #edaece #osmaniauniversity #vlsi #digitalelectronics

2. CMOS AND GATE #ece #tmsy #microwind #edaece #osmaniauniversity #vlsi #digitalelectronics

Experiment 2 || Full Adder || Full Adder using Two Half Adders || EDA LAB || 7th SEM || #TMSY

Experiment 2 || Full Adder || Full Adder using Two Half Adders || EDA LAB || 7th SEM || #TMSY

Experiment 2 || Half Adder using Gates || EDA LAB || 7th SEM || ECE || #TMSY

Experiment 2 || Half Adder using Gates || EDA LAB || 7th SEM || ECE || #TMSY

5. CMOS NOR GATE || DSCH || Microwind || EDA LAB || 7th SEM || ECE || #TMSY

5. CMOS NOR GATE || DSCH || Microwind || EDA LAB || 7th SEM || ECE || #TMSY

4. CMOS NAND GATE #microwind #ece #vlsi #osmaniauniversity #engineering #digitalelectronics

4. CMOS NAND GATE #microwind #ece #vlsi #osmaniauniversity #engineering #digitalelectronics

1. CMOS NOT GATE || DSCH || Microwind || EDA LAB || 7th SEM | #ece #edaece #vlsi #osmaniauniversity

1. CMOS NOT GATE || DSCH || Microwind || EDA LAB || 7th SEM | #ece #edaece #vlsi #osmaniauniversity

III SEM || CSE B || Digital Electronics || 24th Nov 2021 || #TMSY

III SEM || CSE B || Digital Electronics || 24th Nov 2021 || #TMSY

III SEM || CSE A || Digital Electronics || 23rd Nov 2021 || #TMSY

III SEM || CSE A || Digital Electronics || 23rd Nov 2021 || #TMSY

III SEM || CSE - B || Digital Electronics || 18th Nov 2021 || # TMSY

III SEM || CSE - B || Digital Electronics || 18th Nov 2021 || # TMSY

Unit 1 || III SEM || CSE - A || Digital Electronics || 16th Nov 2021 || #TMSY

Unit 1 || III SEM || CSE - A || Digital Electronics || 16th Nov 2021 || #TMSY

Unit 1 || III SEM || CSE B || Digital Electronics || 11th Nov 2021 || #TMSY

Unit 1 || III SEM || CSE B || Digital Electronics || 11th Nov 2021 || #TMSY

Write a Verilog HDL program in Hierarchical Structural model for 16:1 Mux realization using 4:1 Mux

Write a Verilog HDL program in Hierarchical Structural model for 16:1 Mux realization using 4:1 Mux

Write Verilog Code for 4:1 MUX using Gate Level Modelling

Write Verilog Code for 4:1 MUX using Gate Level Modelling

Full Adder Gate Level Modelling

Full Adder Gate Level Modelling

MOD 8 Counter Design and Implementation using D FF || DSDV || Unit 3

MOD 8 Counter Design and Implementation using D FF || DSDV || Unit 3

Design & implementation of Mod 8 Counter using JKFF & DFF || PROM || PAL || PLA || Types of Memories

Design & implementation of Mod 8 Counter using JKFF & DFF || PROM || PAL || PLA || Types of Memories

Moore FSM || Partition Minimization Techniques || Mod Counter Design using FF's || #tmsy || #DSDV

Moore FSM || Partition Minimization Techniques || Mod Counter Design using FF's || #tmsy || #DSDV

How to Set Input Voltage for Clipper Circuits || #PDIC_LAB || #AEC_LAB || #DSDV || #TMSY

How to Set Input Voltage for Clipper Circuits || #PDIC_LAB || #AEC_LAB || #DSDV || #TMSY

Positive Clipper with Negative Reference Voltage || #PDIC_LAB || #AEC_LAB || #DSDV || #TMSY

Positive Clipper with Negative Reference Voltage || #PDIC_LAB || #AEC_LAB || #DSDV || #TMSY

Positive Clipper with and without Reference Voltage || #PDIC_LAB || #AEC_LAB || #DSDV || #TMSY

Positive Clipper with and without Reference Voltage || #PDIC_LAB || #AEC_LAB || #DSDV || #TMSY

Analysis of Clocked Synchronous Sequential Circuit || Unit 3 || #DSDV ||#tmsy

Analysis of Clocked Synchronous Sequential Circuit || Unit 3 || #DSDV ||#tmsy

Synthesis of Synchronous Sequential Circuit || Mealy FSM || Detect Sequence 1010 | #DSDV || #tmsy

Synthesis of Synchronous Sequential Circuit || Mealy FSM || Detect Sequence 1010 | #DSDV || #tmsy

Counters || Asynchronous || Synchronous || Verilog Codes of Counters || #tmsy

Counters || Asynchronous || Synchronous || Verilog Codes of Counters || #tmsy

Unit 5 || Operational Amplifiers || AE || 8th July 2021 || #TMSY

Unit 5 || Operational Amplifiers || AE || 8th July 2021 || #TMSY

Verilog Codes of 4X2 Priority Encoder || Decimal to BCD || Octal to Binary Priority Encoder | #tmsy

Verilog Codes of 4X2 Priority Encoder || Decimal to BCD || Octal to Binary Priority Encoder | #tmsy

DSDV || Digital System Design using Verilog || 17th June 2021 || #tmsy

DSDV || Digital System Design using Verilog || 17th June 2021 || #tmsy

BCD ADDER || DSDV || Digital System Design using Verilog || 12th June 2021 || Session || #tmsy

BCD ADDER || DSDV || Digital System Design using Verilog || 12th June 2021 || Session || #tmsy

2:1 MUX || Short Video || DSDV

2:1 MUX || Short Video || DSDV

DSDV || Digital System Design using Verilog || 10th June 2021 || Session || #tmsy

DSDV || Digital System Design using Verilog || 10th June 2021 || Session || #tmsy

DSDV || Digital System Design using Verilog || 7th June 2021 || Session || #tmsy

DSDV || Digital System Design using Verilog || 7th June 2021 || Session || #tmsy

Switch Level Modelling || #tmsy

Switch Level Modelling || #tmsy

Write Structural Verilog HDL Code for 4-Bit Ripple Carry Adder

Write Structural Verilog HDL Code for 4-Bit Ripple Carry Adder

HALF ADDER || Behavioural Modelling

HALF ADDER || Behavioural Modelling

HALF ADDER || Data Flow Modelling

HALF ADDER || Data Flow Modelling

HALF ADDER || Gate Level Modelling

HALF ADDER || Gate Level Modelling

Working of Half Adder || DSDV || DLD || STLD || Digital Electronics

Working of Half Adder || DSDV || DLD || STLD || Digital Electronics

NAND GATE || All Styles of Modelling

NAND GATE || All Styles of Modelling

NAND GATE || Behavioural Modelling

NAND GATE || Behavioural Modelling

NAND GATE || Data Flow Modelling

NAND GATE || Data Flow Modelling

NAND GATE || Gate Level Modelling

NAND GATE || Gate Level Modelling

Working of NAND GATE || DLD || STLD || Digital Electronics || DSDV LAB

Working of NAND GATE || DLD || STLD || Digital Electronics || DSDV LAB

NOT GATE || All Styles of Modelling

NOT GATE || All Styles of Modelling

NOT GATE || Behavioural Modelling

NOT GATE || Behavioural Modelling

NOT GATE || Data Flow Modelling

NOT GATE || Data Flow Modelling

NOT GATE || Gate Level Modelling

NOT GATE || Gate Level Modelling

Applications of PN Diode || Analog Electronics || EEE Dept || 3rd SEM

Applications of PN Diode || Analog Electronics || EEE Dept || 3rd SEM

OR GATE || All Styles of Modelling

OR GATE || All Styles of Modelling

OR GATE || Behavioural Modelling

OR GATE || Behavioural Modelling

OR GATE || Data Flow Modelling

OR GATE || Data Flow Modelling

OR GATE || Gate Level Modelling || #dsdv

OR GATE || Gate Level Modelling || #dsdv

AND GATE || All Styles of Modelling|| Gate Level Modelling || Data Flow || Behavioural #dsdv #ece

AND GATE || All Styles of Modelling|| Gate Level Modelling || Data Flow || Behavioural #dsdv #ece

DSDV || Digital System Design using Verilog || 6th May 2021 || Session 11|| #tmsy

DSDV || Digital System Design using Verilog || 6th May 2021 || Session 11|| #tmsy

DSDV || Digital System Design using Verilog || 5th May 2021 || Session 10 || #tmsy

DSDV || Digital System Design using Verilog || 5th May 2021 || Session 10 || #tmsy

Structured Procedures || Initial Statement || Always Statement || Sequential and Parallel Blocks

Structured Procedures || Initial Statement || Always Statement || Sequential and Parallel Blocks

DSDV || Digital System Design using Verilog || 24th April 2021 || Session 4|| #tmsy

DSDV || Digital System Design using Verilog || 24th April 2021 || Session 4|| #tmsy

DSDV || Digital System Design using Verilog || 22nd April 2021 || Session 3 || #tmsy

DSDV || Digital System Design using Verilog || 22nd April 2021 || Session 3 || #tmsy

DSDV || Digital System Design using Verilog || 9th April 2021 || Session 2|| #tmsy

DSDV || Digital System Design using Verilog || 9th April 2021 || Session 2|| #tmsy

DSDV || Digital System Design using Verilog || 8th April 2021 || Session 1|| #tmsy

DSDV || Digital System Design using Verilog || 8th April 2021 || Session 1|| #tmsy

Block Diagram Reduction Techniques || Lecture in Telugu || Control Systems || Osmania University

Block Diagram Reduction Techniques || Lecture in Telugu || Control Systems || Osmania University

Colpitts Oscillator || #BE_LAB ||#AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Colpitts Oscillator || #BE_LAB ||#AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

AE || 4th Sep 2020 || Temp Effect on Forward Bias & Reverse Bias || PN Diode Applications

AE || 4th Sep 2020 || Temp Effect on Forward Bias & Reverse Bias || PN Diode Applications

AE || 2nd SEP 2020 || Mass Action Law || V-I Characteristics of PN Junction diode

AE || 2nd SEP 2020 || Mass Action Law || V-I Characteristics of PN Junction diode

Lab 1 - 29th Dec 2020 || Analog Electronics || LAB

Lab 1 - 29th Dec 2020 || Analog Electronics || LAB

2nd Jan 2021

2nd Jan 2021

2nd Jan 2021 || Analog Electronics || UNIT 2 || TMSY

2nd Jan 2021 || Analog Electronics || UNIT 2 || TMSY

28th Dec 2020 || Analog Electronics || TMSY

28th Dec 2020 || Analog Electronics || TMSY

MCET || 12th Oct 2020 || Analog Electronics

MCET || 12th Oct 2020 || Analog Electronics

8th Oct 2020 || Session 23,24 || 11:20 AM to 1:00 PM || Analog Electronics

8th Oct 2020 || Session 23,24 || 11:20 AM to 1:00 PM || Analog Electronics

5th Oct 2020 || Session 21,22 || 10:20 AM to 12:10 PM || Analog Electronics

5th Oct 2020 || Session 21,22 || 10:20 AM to 12:10 PM || Analog Electronics

MCET || 28th Sep 2020 || 10:20 AM to 12:10 PM || Session 18,19 || Analog Electronics

MCET || 28th Sep 2020 || 10:20 AM to 12:10 PM || Session 18,19 || Analog Electronics

MCET || 26th Sep 2020 || 12:10 PM to 1:00 PM || Session 17 || Analog Electronics

MCET || 26th Sep 2020 || 12:10 PM to 1:00 PM || Session 17 || Analog Electronics

MCET || 21st Sep 2020 || 10:20 AM to 12:10 PM || Session 15,16 || Analog Electronics

MCET || 21st Sep 2020 || 10:20 AM to 12:10 PM || Session 15,16 || Analog Electronics

MCET || 19th Sep 2020 || || Session 14 || 12:10 PM to 01:00 PM || Analog Electronics

MCET || 19th Sep 2020 || || Session 14 || 12:10 PM to 01:00 PM || Analog Electronics

MCET || 14th Sep 2020 || Analog Electronics || Session 12,13

MCET || 14th Sep 2020 || Analog Electronics || Session 12,13

LC Oscillator || Hartley Oscillator || #BE_LAB || #AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

LC Oscillator || Hartley Oscillator || #BE_LAB || #AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Full Wave Rectifier without Filter || #AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Full Wave Rectifier without Filter || #AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Working of Function Generator ||#AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Working of Function Generator ||#AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Analog Electronics Unit 2 || 21st Dec 2020

Analog Electronics Unit 2 || 21st Dec 2020

6th jan 2021 || Unit 3 || Feedback Amplifiers

6th jan 2021 || Unit 3 || Feedback Amplifiers

4th Jan 2021 || Analog Electronics || TMSY

4th Jan 2021 || Analog Electronics || TMSY

EXPERIMENT NO 1 || VI CHARACTERISTICS OF SI DIODE AND MEASUREMENT OF STATIC AND DYNAMIC RESISTANCE

EXPERIMENT NO 1 || VI CHARACTERISTICS OF SI DIODE AND MEASUREMENT OF STATIC AND DYNAMIC RESISTANCE

Working of CRO || #AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Working of CRO || #AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Working of Regulated Power Supply ||#AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

Working of Regulated Power Supply ||#AEC_LAB || #PDIC_LAB || #DSDV || #TMSY

EXPERIMENT: 10 || NON-INVERTING AMPLIFIER USING OP-AMP || MCET ||

EXPERIMENT: 10 || NON-INVERTING AMPLIFIER USING OP-AMP || MCET ||

AE || 11th Sep 2020 || Center Tapped Full Wave Rectifier || Parameters of Center Tapped Full Wave

AE || 11th Sep 2020 || Center Tapped Full Wave Rectifier || Parameters of Center Tapped Full Wave

EXPERIMENT 09 || INVERTING AMPLIFIER USING OP-AMP || MCET

EXPERIMENT 09 || INVERTING AMPLIFIER USING OP-AMP || MCET

Write Structural & Dataflow Verilog HDL Code for 16-bit Ripple Carry Adder

Write Structural & Dataflow Verilog HDL Code for 16-bit Ripple Carry Adder

How to Evaluate Internal 1 Papers via Hiremee || MCET || Part 1

How to Evaluate Internal 1 Papers via Hiremee || MCET || Part 1