Канал: Digital2Real Tutorials

System verilog constraint question sol 2, randomize 16 bit var,consecutive 2 bits are 1, rest 0

System verilog constraint question sol 2, randomize 16 bit var,consecutive 2 bits are 1, rest 0

System verilog constraint interview question so 1, randomize 16 bit var, consecutive 2 bits 1 rest 0

System verilog constraint interview question so 1, randomize 16 bit var, consecutive 2 bits 1 rest 0

Implement randc function in systemverilog without using randc keyword #systemverilog

Implement randc function in systemverilog without using randc keyword #systemverilog

System verilog interview question, count number of ones #systemverilog

System verilog interview question, count number of ones #systemverilog

GATE EC 2021 Quantative Aptitude

GATE EC 2021 Quantative Aptitude

GATE Electrical 2021 Quantative Aptitude Question

GATE Electrical 2021 Quantative Aptitude Question

virtual function in systemverilog #systemverilog

virtual function in systemverilog #systemverilog

foreach loop for system verilog explained with examples #systemverilog

foreach loop for system verilog explained with examples #systemverilog

System Verilog randomization methods, pre_randomize() and post_randomize ()#systemverilog

System Verilog randomization methods, pre_randomize() and post_randomize ()#systemverilog

Introduction to coverage driven verification methodology #systemverilog

Introduction to coverage driven verification methodology #systemverilog

casex in verilog #verilog

casex in verilog #verilog

casez statement in Verilog #verilog

casez statement in Verilog #verilog

Interface in System Verilog #systemverilog

Interface in System Verilog #systemverilog

Randomization in System Verilog #systemverilog

Randomization in System Verilog #systemverilog

Mailbox in System Verilog/Explained with its handle in Generator and Driver Classes #systemverilog

Mailbox in System Verilog/Explained with its handle in Generator and Driver Classes #systemverilog

Components of System Verilog Testbench /Transaction Class and Generator Class explained with example

Components of System Verilog Testbench /Transaction Class and Generator Class explained with example

What is System Verilog?OOPs Concepts(Class, Abstraction,Encapsulation,inhertance,Polymorphism)in HVL

What is System Verilog?OOPs Concepts(Class, Abstraction,Encapsulation,inhertance,Polymorphism)in HVL

Verilog Code of Sequence Detector/Mealy FSM/Overlapping Sequence Detector #digitalelectronics

Verilog Code of Sequence Detector/Mealy FSM/Overlapping Sequence Detector #digitalelectronics

VI Editor commands in Linux

VI Editor commands in Linux

GATE CS 2019/Boolean Algebra/sum of products/AND gate XOR gate /use of set theory (intersection)

GATE CS 2019/Boolean Algebra/sum of products/AND gate XOR gate /use of set theory (intersection)

GATE CS 2015/Boolean Algebra/K Map #gatecs2022

GATE CS 2015/Boolean Algebra/K Map #gatecs2022

GATE CS 2014/Boolean Algebra/K map #gatecs2022

GATE CS 2014/Boolean Algebra/K map #gatecs2022

Overview of Linux Operating system/Difference between Linux and Unix/Introduced vi editor#linux

Overview of Linux Operating system/Difference between Linux and Unix/Introduced vi editor#linux

Cycle Accurate Simulator #simulation tools

Cycle Accurate Simulator #simulation tools

Design of Overlapping sequence detector/Sequence Detector Part 2 #sequentialcircuit

Design of Overlapping sequence detector/Sequence Detector Part 2 #sequentialcircuit

Concept of Overlapping and Non- overlapping sequence detection/Sequence detector Part -1

Concept of Overlapping and Non- overlapping sequence detection/Sequence detector Part -1

4 Bit Parallel Adder / Substractor circuit #digitalelectronics

4 Bit Parallel Adder / Substractor circuit #digitalelectronics

GATE CS 2003/Operations by choosing K & C0/2 bit parallel adder for 2s complement subtraction #gate

GATE CS 2003/Operations by choosing K & C0/2 bit parallel adder for 2s complement subtraction #gate

Verilog Scheduling Semantics #verilog

Verilog Scheduling Semantics #verilog

Verilog code of Carry Look Ahead Adder #verilog

Verilog code of Carry Look Ahead Adder #verilog

Verilog generate if and generate case blocks #verilog

Verilog generate if and generate case blocks #verilog

Verilog Generate Block/"generate for" loop explained with examples #verilog

Verilog Generate Block/"generate for" loop explained with examples #verilog

GATE EC 2022/Select the Boolean function(s) equivalent to x+yz, where x,y and z are Boolean variable

GATE EC 2022/Select the Boolean function(s) equivalent to x+yz, where x,y and z are Boolean variable

GATE EC 2022/Consider a MUX shown, OUTPUT to be XOR of C and D,the values of A0, A1, A2 and A3 are..

GATE EC 2022/Consider a MUX shown, OUTPUT to be XOR of C and D,the values of A0, A1, A2 and A3 are..

Carry Look Ahead Adder (CLA)#combinationalcircuit co

Carry Look Ahead Adder (CLA)#combinationalcircuit co

Design a combinational circuit which converts code from 84-2-1 to 8421 code #digitalelectronics

Design a combinational circuit which converts code from 84-2-1 to 8421 code #digitalelectronics

Combinational circuit, 3 INs & 1 OUT, Output 1 when binary value is less than 3 otherwise 0

Combinational circuit, 3 INs & 1 OUT, Output 1 when binary value is less than 3 otherwise 0

Difference of Verilog and VHDL in low-level modeling

Difference of Verilog and VHDL in low-level modeling

Hurry up solve it fast!! ISRO CS 2020/Carry Pd of each full adder ?#Rippleadder

Hurry up solve it fast!! ISRO CS 2020/Carry Pd of each full adder ?#Rippleadder

Hurry up solve it fast!!! GATE CS 2015/Proportion delay of 4 bit Ripple carry adder

Hurry up solve it fast!!! GATE CS 2015/Proportion delay of 4 bit Ripple carry adder

GATE EC 2014/Worst case delay of 16 bit Ripple Carry Adder?Carry Pd 1 FA 12ns , Sum Pd 1 FA 15ns

GATE EC 2014/Worst case delay of 16 bit Ripple Carry Adder?Carry Pd 1 FA 12ns , Sum Pd 1 FA 15ns

How 🤔 ❓ to find worse case delay in Ripple Carry Adder

How 🤔 ❓ to find worse case delay in Ripple Carry Adder

GATE CS 2014/COA/Decimal to IEEE 754 single precision floating point format #gateexam

GATE CS 2014/COA/Decimal to IEEE 754 single precision floating point format #gateexam

GATE CS 2022/COA/IEEE 754 Single Precision Floating Point Format to equivalent Decimal value

GATE CS 2022/COA/IEEE 754 Single Precision Floating Point Format to equivalent Decimal value

GATE IT 2004/Overflow For 2s Complement Addition/using 4 bit 2s Complement arithmetic,which.......

GATE IT 2004/Overflow For 2s Complement Addition/using 4 bit 2s Complement arithmetic,which.......

GATE CS 2022/Arithmetic Overflow For 2s Complement Addition/Let R1 and R2 be two 4 bit registers ...

GATE CS 2022/Arithmetic Overflow For 2s Complement Addition/Let R1 and R2 be two 4 bit registers ...

ISRO 2008/Number System/Digital Electronics

ISRO 2008/Number System/Digital Electronics

'ifdef compiler directive VERILOG #verilog

'ifdef compiler directive VERILOG #verilog

I2C Bus Arbitration #i2c

I2C Bus Arbitration #i2c

Operation of I2C/structure of message(start address frame, R/W bit, ACK, NACK bit, DATA frame, stop)

Operation of I2C/structure of message(start address frame, R/W bit, ACK, NACK bit, DATA frame, stop)

Overview Of I2C Bus PROTOCOL #i2c

Overview Of I2C Bus PROTOCOL #i2c

GATE CS 2004/Control Memory/Processor/Microinstruction Question #gatecs2022

GATE CS 2004/Control Memory/Processor/Microinstruction Question #gatecs2022

Verilog Code of Booth's Multiplication Algorithm#verilog

Verilog Code of Booth's Multiplication Algorithm#verilog

How many additions & subtractions needed for multiplication of these two numbers?Booth's Algorithm

How many additions & subtractions needed for multiplication of these two numbers?Booth's Algorithm

GATE IT 2008 Question on Booth's Multiplication Algorithm

GATE IT 2008 Question on Booth's Multiplication Algorithm

Booth's Multiplication Algorithm for signed numbers/ -3x-7=21 multiplication #booth multiplication

Booth's Multiplication Algorithm for signed numbers/ -3x-7=21 multiplication #booth multiplication

Design combinational circuit/4 bit Bin Input & Output 2s Complement of input #combinationalcircuit

Design combinational circuit/4 bit Bin Input & Output 2s Complement of input #combinationalcircuit

Beautiful 😍 storage box craft made by my daughter ❤

Beautiful 😍 storage box craft made by my daughter ❤

GATE CS 2004/If size of transfer is 20 Kbytes .What is the percent of processor time consumed ...

GATE CS 2004/If size of transfer is 20 Kbytes .What is the percent of processor time consumed ...

GATE CS 2021/If 0.5 percent processor cycles are used for DMA,data transfer rate of the device is ?

GATE CS 2021/If 0.5 percent processor cycles are used for DMA,data transfer rate of the device is ?

DMA Question 2/what is percentage of time CPU is busy to transfer 16MB of data from I/O to memory

DMA Question 2/what is percentage of time CPU is busy to transfer 16MB of data from I/O to memory

DMA Question 1/Min num of times DMA Controller needs to get control of system bus from processor....

DMA Question 1/Min num of times DMA Controller needs to get control of system bus from processor....

DMA Controller in Computer Architecture

DMA Controller in Computer Architecture

GATE ECE 2018/Minimum number of Flip flips to implement traffic signal cycles FSM

GATE ECE 2018/Minimum number of Flip flips to implement traffic signal cycles FSM

Verilog RTL Code and Testbench of Newspaper Vending machine /Moore FSM example #verilog

Verilog RTL Code and Testbench of Newspaper Vending machine /Moore FSM example #verilog

Verilog RTL code and Testbench code of 16 STAGES, 8 BIT DATA WIDTH SYNCHRONOUS FIFO MEMORY #verilog

Verilog RTL code and Testbench code of 16 STAGES, 8 BIT DATA WIDTH SYNCHRONOUS FIFO MEMORY #verilog

How to write a testbench in Verilog/Difference between simulation and synthesis #verilog

How to write a testbench in Verilog/Difference between simulation and synthesis #verilog

Verilog Code Of Priority Encoder #verilog

Verilog Code Of Priority Encoder #verilog

Design And Timing Analysis of 4x4 Array Multiplier/Generalized Equations For MxN Array Multiplier

Design And Timing Analysis of 4x4 Array Multiplier/Generalized Equations For MxN Array Multiplier

Verilog Code Of Single Port RAM with Synchronous READ/WRITE

Verilog Code Of Single Port RAM with Synchronous READ/WRITE

UGC NET 2008 Question on Multiplexers where four 4 input muxes are driving 4 inputs of a 4x1 mux

UGC NET 2008 Question on Multiplexers where four 4 input muxes are driving 4 inputs of a 4x1 mux

ISRO 2007 Question on Combinational Circuit Output (Circuit made of NOR gates)

ISRO 2007 Question on Combinational Circuit Output (Circuit made of NOR gates)

UGC NET 2006 Question on Combinational Circuit #digitalelectronics

UGC NET 2006 Question on Combinational Circuit #digitalelectronics

UGC NET CS 2009 Question on Switching function implementation using Multiplexer

UGC NET CS 2009 Question on Switching function implementation using Multiplexer

ISRO 2016/HALF SUBSTRACTOR QUESTION

ISRO 2016/HALF SUBSTRACTOR QUESTION

HALF SUBSTRACTOR #digitalelectronics

HALF SUBSTRACTOR #digitalelectronics

Verilog Code of 4x4 Bit Array Multiplier

Verilog Code of 4x4 Bit Array Multiplier

ARRAY MULTIPLIER/4x4 BIT MULTIPLIER#combinationalcircuit

ARRAY MULTIPLIER/4x4 BIT MULTIPLIER#combinationalcircuit

Array Multiplier/ 2x2 Multiplier #combinationalcircuit

Array Multiplier/ 2x2 Multiplier #combinationalcircuit

Verilog Code of Clock Generator with TB to generate CLK with Varying Frequency,Phase & Duty Cycle

Verilog Code of Clock Generator with TB to generate CLK with Varying Frequency,Phase & Duty Cycle

Multiplication using Shift and Add method Algorithm

Multiplication using Shift and Add method Algorithm

Decimal to Gray conversion example #numbersystem

Decimal to Gray conversion example #numbersystem

MCQs on PROGRAMABLE LOGIC DEVICES

MCQs on PROGRAMABLE LOGIC DEVICES

Programmable Logic Array (PLA)

Programmable Logic Array (PLA)

GATE EC 2017/PLA is shown in figure, find Boolean function F implemented is ?

GATE EC 2017/PLA is shown in figure, find Boolean function F implemented is ?

DESIGN OF GRAY CODE TO BINARY CODE CONVERTER #digitalelectronics

DESIGN OF GRAY CODE TO BINARY CODE CONVERTER #digitalelectronics

Design of Binary to Gray Code Converter

Design of Binary to Gray Code Converter

Design of BCD to Excess 3 code converter with logic gates#digitalelectronics

Design of BCD to Excess 3 code converter with logic gates#digitalelectronics

Coloring Activity of my 7 years old 💘

Coloring Activity of my 7 years old 💘

EXCESS 3 CODE, XS-3 to BCD CONVERSION AND SELF COMPLEMENTING NATURE OF XS-3 CODE

EXCESS 3 CODE, XS-3 to BCD CONVERSION AND SELF COMPLEMENTING NATURE OF XS-3 CODE

GATE CSE 2006/h3h3h1h0 gray code of num n & g3g2g1g0 gray of num (n+1)mod16.Which function correct?

GATE CSE 2006/h3h3h1h0 gray code of num n & g3g2g1g0 gray of num (n+1)mod16.Which function correct?

Gray Code to Binary Code Conversion with example #numbersystem

Gray Code to Binary Code Conversion with example #numbersystem

What is Gray Code ?How to convert Binary number to Gray code number?Show with example #numbersystem

What is Gray Code ?How to convert Binary number to Gray code number?Show with example #numbersystem

Implementation of full adder using two 2 to 4 decoders and nand gate

Implementation of full adder using two 2 to 4 decoders and nand gate

Implementation of full adder using 3 to 8 decoder and nand gate

Implementation of full adder using 3 to 8 decoder and nand gate

Design combinational circuit that produces sum of two 2 bit numbers using two full adders #digilogic

Design combinational circuit that produces sum of two 2 bit numbers using two full adders #digilogic

Design a combinational circuit that adds 1 to a 4 bit Binary number using half adders(incrementer)

Design a combinational circuit that adds 1 to a 4 bit Binary number using half adders(incrementer)

ADDERS/HALF ADDER AND FULL ADDER #digitalelectronics

ADDERS/HALF ADDER AND FULL ADDER #digitalelectronics

GATE EC 1998/for the identity Boolean expression find the dual equation

GATE EC 1998/for the identity Boolean expression find the dual equation

GATE EC 2000/Seq. Circuit of D flip flop & logic gate is shown where X and Y are inputs and Z output

GATE EC 2000/Seq. Circuit of D flip flop & logic gate is shown where X and Y are inputs and Z output

MCQs on Embedded Systems

MCQs on Embedded Systems

MCQs on Verilog and System Verilog #verilog

MCQs on Verilog and System Verilog #verilog

MCQ on Boolean Algebra

MCQ on Boolean Algebra

What are min num of 2 :1 mux is required to generate 2 input AND gate and 2 input EX-OR gate?

What are min num of 2 :1 mux is required to generate 2 input AND gate and 2 input EX-OR gate?

GATE EC 2000/Boolean Algebra/For the logic circuit shown in figure, find the Boolean expression?

GATE EC 2000/Boolean Algebra/For the logic circuit shown in figure, find the Boolean expression?

GATE EC 1997/A 2 bit multiplier is implemented with ? which of the gate combinations is correct 🤔

GATE EC 1997/A 2 bit multiplier is implemented with ? which of the gate combinations is correct 🤔

GATE EC 1997/A 2 bit multiplier can be implemented using ?which combination of gates

GATE EC 1997/A 2 bit multiplier can be implemented using ?which combination of gates

GATE EC 2009/Minimum number of 2 to 1 mux to generate a 2 input AND gate and a 2 input EXOR GATE?

GATE EC 2009/Minimum number of 2 to 1 mux to generate a 2 input AND gate and a 2 input EXOR GATE?

GATE EC 2004/minimum no. of 2:1 multiplexer needed to realize a 4:1 multiplexer?

GATE EC 2004/minimum no. of 2:1 multiplexer needed to realize a 4:1 multiplexer?

GATE EC 2013/4 RAM chips of 1024 bytes are connected to 16 bit addr bus, Find mapped addr of RAMs?

GATE EC 2013/4 RAM chips of 1024 bytes are connected to 16 bit addr bus, Find mapped addr of RAMs?

1 to 2 Demultiplexer and 1 to 4 Demultiplexer #digitalelectronics

1 to 2 Demultiplexer and 1 to 4 Demultiplexer #digitalelectronics

GATE EC 2003/PIPO/ROM/4 bit PIPO reg out feed 16x4 ROM input, out of ROM feed data bus,partial ROM..

GATE EC 2003/PIPO/ROM/4 bit PIPO reg out feed 16x4 ROM input, out of ROM feed data bus,partial ROM..

GATE EC 2003/PIPO/ROM/Output of PIPO connected to 16x4 ROM, Out of ROM loads data bus,partial ROM...

GATE EC 2003/PIPO/ROM/Output of PIPO connected to 16x4 ROM, Out of ROM loads data bus,partial ROM...

Memory Refresh Operation DRAM

Memory Refresh Operation DRAM

GATE CS 2018/Percentage of time for memory rd/wr w.r.t Refresh period(2ms) of DRAM of 2^14 Rows ?

GATE CS 2018/Percentage of time for memory rd/wr w.r.t Refresh period(2ms) of DRAM of 2^14 Rows ?

GATE CSE 2012/ The amount of ROM needed to implement a 4 bit multiplier is ?

GATE CSE 2012/ The amount of ROM needed to implement a 4 bit multiplier is ?

GATE IT 2004/Min size of ROM required to store complete Truth table of 8 bit x 8 bit multiplier ?

GATE IT 2004/Min size of ROM required to store complete Truth table of 8 bit x 8 bit multiplier ?

(7,4)Hamming code is used.If msg 0001 is mapped to code 0000111 and msg 0011 is mapped to 1100110..

(7,4)Hamming code is used.If msg 0001 is mapped to code 0000111 and msg 0011 is mapped to 1100110..

GATE 2019 EC/Linear hamming code is used to map 4 bit msg to 7 bit code,0001 mapped to 0000111...

GATE 2019 EC/Linear hamming code is used to map 4 bit msg to 7 bit code,0001 mapped to 0000111...

DATAFLOW MODELING IN VERILOG PART 1

DATAFLOW MODELING IN VERILOG PART 1

GATE 2015 /16KB=16384 bits memory array designed as a square , addr lines for row decoder ?

GATE 2015 /16KB=16384 bits memory array designed as a square , addr lines for row decoder ?

GATE 2004 ECE/11001,1001 & 111001 are 2's complement representation of which set of numbers?

GATE 2004 ECE/11001,1001 & 111001 are 2's complement representation of which set of numbers?

MCQ on Boolean Algebra/w,x,y,z are Boolean variables then which one of the following is INCORRECT?

MCQ on Boolean Algebra/w,x,y,z are Boolean variables then which one of the following is INCORRECT?

GATE 2018/Boolean Algebra/Boolean expressions have XOR and XNOR operations,then which eq. INCORRECT?

GATE 2018/Boolean Algebra/Boolean expressions have XOR and XNOR operations,then which eq. INCORRECT?

MCQs on VHDL/Questions and Answers on EDA tools #EDAtool

MCQs on VHDL/Questions and Answers on EDA tools #EDAtool

GATE 2014/Out device interfaced with microprocessor.Interfacing circuit 3x8 decoder. Addr of device?

GATE 2014/Out device interfaced with microprocessor.Interfacing circuit 3x8 decoder. Addr of device?

GATE 2014/Output device is interface with microprocessor,interfacing cir 3x8 decoder,addr of device?

GATE 2014/Output device is interface with microprocessor,interfacing cir 3x8 decoder,addr of device?

30 Digital Electronics Mcqs #digitalelectronics

30 Digital Electronics Mcqs #digitalelectronics

ASIC Design Flow PART 2

ASIC Design Flow PART 2

ASIC Design Flow PART 1

ASIC Design Flow PART 1

GATE DELAYS IN VERILOG #verilog

GATE DELAYS IN VERILOG #verilog

GATE 2009 EC/What are counting states for (Q1,Q2), for the counter shown (formed from JK flip flops)

GATE 2009 EC/What are counting states for (Q1,Q2), for the counter shown (formed from JK flip flops)

GATE 2009 EC/ What are the counting states of counter shown (formed from two JK flip flops )?

GATE 2009 EC/ What are the counting states of counter shown (formed from two JK flip flops )?

GATE 2010 EC/74LS138 3 to 8 Decoder where Y5 is selected and addr range ?#gateexam

GATE 2010 EC/74LS138 3 to 8 Decoder where Y5 is selected and addr range ?#gateexam

GATE 2010 EC paper/74LS138, 3 to 8 Decoder Question where output Y5 is to be selected, addr range?

GATE 2010 EC paper/74LS138, 3 to 8 Decoder Question where output Y5 is to be selected, addr range?

MCQ on PISO shift registers feeding FA, output of FA ?

MCQ on PISO shift registers feeding FA, output of FA ?

MCQ on K-Map/Boolean Algebra/Find number of product terms in minimized SOP expression?

MCQ on K-Map/Boolean Algebra/Find number of product terms in minimized SOP expression?

Number of product terms in the minimized SOP obtained through K map is (where d denotes don't care)?

Number of product terms in the minimized SOP obtained through K map is (where d denotes don't care)?

Two PISO shift registers loaded with data feed to FA, o/p of FA after 2 clks?#digitalelectronics

Two PISO shift registers loaded with data feed to FA, o/p of FA after 2 clks?#digitalelectronics

GATE LEVEL MODELING OF 4 BIT RIPPLE CARRY FULL ADDER IN VERILOG#verilog

GATE LEVEL MODELING OF 4 BIT RIPPLE CARRY FULL ADDER IN VERILOG#verilog

Gate level modeling of 4:1 Multiplexer in Verilog

Gate level modeling of 4:1 Multiplexer in Verilog

GATE LEVEL MODELING IN VERILOG

GATE LEVEL MODELING IN VERILOG

GATE 2010 ECE/Boolean function is realized by 4 : 1 Mux , the function F(A,B,C,D) = ?

GATE 2010 ECE/Boolean function is realized by 4 : 1 Mux , the function F(A,B,C,D) = ?

GATE 2010 ECE/Boolean function is realized by a 4 : 1 Mux , the function F(A,B,C,D)=which minterms?

GATE 2010 ECE/Boolean function is realized by a 4 : 1 Mux , the function F(A,B,C,D)=which minterms?

GATE EC/NAND and NOR latches Question/initially (0,1)applied to inputsof latches,then (1,1),outputs?

GATE EC/NAND and NOR latches Question/initially (0,1)applied to inputsof latches,then (1,1),outputs?

GATE EC/NAND and NOR Latches Question/(0,1)inputs are applied initially to latches then(1,1)Outputs?

GATE EC/NAND and NOR Latches Question/(0,1)inputs are applied initially to latches then(1,1)Outputs?

GATE 2008/4x1 Mux Question/Boolean Algebra/K map simplification

GATE 2008/4x1 Mux Question/Boolean Algebra/K map simplification

GATE 2008/Boolean Algebra /K map/I0 to I3 inputs to 4 to 1 mux, R(msb) and S ctrl bits, out Z ?

GATE 2008/Boolean Algebra /K map/I0 to I3 inputs to 4 to 1 mux, R(msb) and S ctrl bits, out Z ?

Port in Verilog #verilog

Port in Verilog #verilog

Components of module block in Verilog #verilog

Components of module block in Verilog #verilog

For the output F to be 1, in the logic circuit, the input combination should be?#digitalelectronics

For the output F to be 1, in the logic circuit, the input combination should be?#digitalelectronics

System Tasks and Compiler Directives in Verilog #verilog

System Tasks and Compiler Directives in Verilog #verilog

GATE 2010 ECE MCQ/For the output F to be 1 in logic circuit, input combination ?#digitalelectronics

GATE 2010 ECE MCQ/For the output F to be 1 in logic circuit, input combination ?#digitalelectronics

Datatypes in Verilog #verilog

Datatypes in Verilog #verilog

GATE ECE 2002/Input to digital circuit consisting of cascade of 20 XOR gates is X,Output?#gateexam

GATE ECE 2002/Input to digital circuit consisting of cascade of 20 XOR gates is X,Output?#gateexam

GATE 2000 ECE/The logic circuit(NAND,NOR gates), simplified boolean expression for the output Y is?

GATE 2000 ECE/The logic circuit(NAND,NOR gates), simplified boolean expression for the output Y is?

GATE 2000 ECE/The logic circuit(XOR,XNOR,AND gates)the input condition A,B,C to make output X=1?

GATE 2000 ECE/The logic circuit(XOR,XNOR,AND gates)the input condition A,B,C to make output X=1?

Lexical conventions in Verilog #verilog

Lexical conventions in Verilog #verilog

GATE 2013/Quine Mcluskey 3 variables Tabular Meth/In SOP,f(x,y,z)= sigma(2,3,4,5),prime implicants?

GATE 2013/Quine Mcluskey 3 variables Tabular Meth/In SOP,f(x,y,z)= sigma(2,3,4,5),prime implicants?

GATE 2011 EC Question Solution/Output Y in the circuit (of all NAND gates) is always 1 when

GATE 2011 EC Question Solution/Output Y in the circuit (of all NAND gates) is always 1 when

GATE 2012 EC Paper Question Solution on State Transition Diagram #gateexam #digitalelectronics

GATE 2012 EC Paper Question Solution on State Transition Diagram #gateexam #digitalelectronics

GATE 2012 EC paper Question Solution on Race Around Condition/Twisted Question on SR flip flop

GATE 2012 EC paper Question Solution on Race Around Condition/Twisted Question on SR flip flop

Design combinational circuit for 3 bit Binary number as input and square of it as output

Design combinational circuit for 3 bit Binary number as input and square of it as output

Quine Mcluskey Tabular Method of 4 variables (Boolean function minimization method) #digitallogic

Quine Mcluskey Tabular Method of 4 variables (Boolean function minimization method) #digitallogic

Mealy and Moore Finite State Machines #digitalelectronics

Mealy and Moore Finite State Machines #digitalelectronics

GATE 2021 IN Engineering Q IN 23 Solution/Sychronous Sequential Circuit with JK FF& T FF #flipflops

GATE 2021 IN Engineering Q IN 23 Solution/Sychronous Sequential Circuit with JK FF& T FF #flipflops

GATE 2021 Intrumentation engineering Question 14 solution (memory mapping) #memories

GATE 2021 Intrumentation engineering Question 14 solution (memory mapping) #memories

GATE 2021 Intrumentation Engineering Question 22 Solution #gateexam #booleanalgebra

GATE 2021 Intrumentation Engineering Question 22 Solution #gateexam #booleanalgebra

GATE 2020 IN/Boolean Operation performed by following circuit at the output Q is ?

GATE 2020 IN/Boolean Operation performed by following circuit at the output Q is ?

GATE 2020 IN/f(A,B,C,D)=sig m(0,1,2,6,8,9,10,11)+sig d(3,7,14,15) is a Boolean func, min SOP exp. F?

GATE 2020 IN/f(A,B,C,D)=sig m(0,1,2,6,8,9,10,11)+sig d(3,7,14,15) is a Boolean func, min SOP exp. F?

GATE 2020 Electronics & Commun. Engg . paper Question EC 10 #gateexam #multiplexers

GATE 2020 Electronics & Commun. Engg . paper Question EC 10 #gateexam #multiplexers

In 8085 CSbar generated by addr lines A15-A10 through 6 input NAND gate.for CC00-CFFF, inputs?#8085

In 8085 CSbar generated by addr lines A15-A10 through 6 input NAND gate.for CC00-CFFF, inputs?#8085

Non Blocking Assignment explanation with example #verilog

Non Blocking Assignment explanation with example #verilog

Blocking vs Non blocking Assignment in Verilog #verilog

Blocking vs Non blocking Assignment in Verilog #verilog

Verilog code of RTL and testbench of D flip flop with asynchronous high reset #verilog

Verilog code of RTL and testbench of D flip flop with asynchronous high reset #verilog

Edge triggered synchronous binary counter has CLK & CLR bar , L & C. correct matching between A & B?

Edge triggered synchronous binary counter has CLK & CLR bar , L & C. correct matching between A & B?

Boolean function F(A,B,C) = pos(0,2,4,7) is to be realized with 4x1 mux . Find ans from options

Boolean function F(A,B,C) = pos(0,2,4,7) is to be realized with 4x1 mux . Find ans from options

X=01110 & Y = 11001 are 5 bit Binary numbers in 2's complement form. Find X + Y in 2's complement

X=01110 & Y = 11001 are 5 bit Binary numbers in 2's complement form. Find X + Y in 2's complement

Combinational circuit 2 bit Binary num input and output its square in binary.Design circuit with ROM

Combinational circuit 2 bit Binary num input and output its square in binary.Design circuit with ROM

ISRO 2013/binary nums in signed 2's complement P=11100110 & Q=11100110,P-Q in signed 2's complement?

ISRO 2013/binary nums in signed 2's complement P=11100110 & Q=11100110,P-Q in signed 2's complement?

The two numbers in signed 2's complement form are P & Q . If P-Q, value in 2's complement form ?

The two numbers in signed 2's complement form are P & Q . If P-Q, value in 2's complement form ?

Verilog RTL and TB codes of JK flip flop with description of the building blocks #verilog

Verilog RTL and TB codes of JK flip flop with description of the building blocks #verilog

Combinational circuit of 2 bit input and output( input ^2). Design the circuit with min size ROM

Combinational circuit of 2 bit input and output( input ^2). Design the circuit with min size ROM

The minimized form of the Boolean expression F(A,B,C) = pi(0,2,3) I.e. pos(0,2,3) is

The minimized form of the Boolean expression F(A,B,C) = pi(0,2,3) I.e. pos(0,2,3) is

The 2's complement of the binary number 1101100 in BCD is ? Find ans from options

The 2's complement of the binary number 1101100 in BCD is ? Find ans from options

Digital Electronics Questions and Solutions JTO EXAM 2008 PART 1 #digitalelectronics

Digital Electronics Questions and Solutions JTO EXAM 2008 PART 1 #digitalelectronics

Inter Register Transfer in Register Transfer Logic #digitalelectronics #rtl

Inter Register Transfer in Register Transfer Logic #digitalelectronics #rtl

Introduction to Register Transfer Logic #digitalelectronics #rtl

Introduction to Register Transfer Logic #digitalelectronics #rtl

Sequential Signal Assignment VHDL #vhdl

Sequential Signal Assignment VHDL #vhdl

Sequential statements in VHDL Language/process statement/wait statement #digitalelectronics #vhdl

Sequential statements in VHDL Language/process statement/wait statement #digitalelectronics #vhdl

Universal Gate NOR/Boolean function implemented with NOR Gates/GATE question solved #logicgates

Universal Gate NOR/Boolean function implemented with NOR Gates/GATE question solved #logicgates

Duality Principle of Boolean expressions #logicgates #booleanalgebra

Duality Principle of Boolean expressions #logicgates #booleanalgebra

How to Realize a XOR gate with minimum number of NAND GATES #logicgates #digitalelectronics

How to Realize a XOR gate with minimum number of NAND GATES #logicgates #digitalelectronics

NAND Gate Implementation #logicgates #digitalelectronics

NAND Gate Implementation #logicgates #digitalelectronics

Binary cell with X and Y select/256 words Memory decoding with two 4x16 Decoders #memories #shorts

Binary cell with X and Y select/256 words Memory decoding with two 4x16 Decoders #memories #shorts

Question on Memory Addr Decoding with Row Decoder (X select) and Column Decoder ( Y select) #memory

Question on Memory Addr Decoding with Row Decoder (X select) and Column Decoder ( Y select) #memory

VHDL code of AND gate / Basic concepts on the design elements of vhdl language #vhdl #hdl

VHDL code of AND gate / Basic concepts on the design elements of vhdl language #vhdl #hdl

Design of 4 x 1 Memory Array / Design of RAM (4 words and 1 bit/word) #memories

Design of 4 x 1 Memory Array / Design of RAM (4 words and 1 bit/word) #memories

What is HDL language? Explained with Verilog code of AND gate example #hdl #verilog

What is HDL language? Explained with Verilog code of AND gate example #hdl #verilog

Latch vs Flip flop #digitalelectronics #memories

Latch vs Flip flop #digitalelectronics #memories