Канал: THE LEARNER

CURRENT STARVED VCO

CURRENT STARVED VCO

RING OSCILLATOR USING LTSPICE

RING OSCILLATOR USING LTSPICE

TWO STAGE OPAMP IN LTSPICE

TWO STAGE OPAMP IN LTSPICE

ONE STAGE OP AMP USING LTSPICE

ONE STAGE OP AMP USING LTSPICE

DIFFERENTIAL AMPLIFIER USING LTSPICE

DIFFERENTIAL AMPLIFIER USING LTSPICE

CASCODE AMPLIFIER USING LTSPICE

CASCODE AMPLIFIER USING LTSPICE

COMMON GATE AMPLIFIER USING LTSPICE

COMMON GATE AMPLIFIER USING LTSPICE

SOURCE FOLLOWER USING LTSPICE

SOURCE FOLLOWER USING LTSPICE

COMMON SOURCE AMPLIFIER WITH DIODE CONNECTED LOAD

COMMON SOURCE AMPLIFIER WITH DIODE CONNECTED LOAD

COMMON SOURCE WITH RESISTIVE LOAD AMPLIFIER

COMMON SOURCE WITH RESISTIVE LOAD AMPLIFIER

WILSON CURRENT MIRROR USING LTSPICE

WILSON CURRENT MIRROR USING LTSPICE

CASCODE CURRENT MIRROR USING LTSPICE

CASCODE CURRENT MIRROR USING LTSPICE

SIMPLE CURRENT MIRROR USING LTSPICE - DC ANALYSIS & AC ANALYSIS

SIMPLE CURRENT MIRROR USING LTSPICE - DC ANALYSIS & AC ANALYSIS

3 Bit SYNCHRONOUS COUNTER

3 Bit SYNCHRONOUS COUNTER

BASIC ADDERS USING LOGISIM

BASIC ADDERS USING LOGISIM

OPAMP- INVERTING, NON-INVERTING, VOLTAGE FOLLOWER USING LTSPICE

OPAMP- INVERTING, NON-INVERTING, VOLTAGE FOLLOWER USING LTSPICE

BIASING CHARACTERISTICS FOR BJT

BIASING CHARACTERISTICS FOR BJT

MOSFET TRANSFER CHARACTERISTICS

MOSFET TRANSFER CHARACTERISTICS

CEAMPLIFIER - TRANSIENT, FREQUENCY RESPONSE

CEAMPLIFIER - TRANSIENT, FREQUENCY RESPONSE

BJT OPERATION (COMMON EMITTER CONFIGURATION)

BJT OPERATION (COMMON EMITTER CONFIGURATION)

BRIDGE RECTIFIER WITH AND WITHOUT FILTER USING LTSPICE

BRIDGE RECTIFIER WITH AND WITHOUT FILTER USING LTSPICE

FULL WAVE RECTIFIER WITH & WITHOUT FILTER USING LTSPICE

FULL WAVE RECTIFIER WITH & WITHOUT FILTER USING LTSPICE

HALF WAVE RECTIFIER WITH AND WITHOUT FILTER

HALF WAVE RECTIFIER WITH AND WITHOUT FILTER

DATA STRUCTURE CONCEPT AND IMPLEMENTATION ( HANDS-ON)

DATA STRUCTURE CONCEPT AND IMPLEMENTATION ( HANDS-ON)

Placement Training on "Python"

Placement Training on "Python"

THE LEARNER Live Stream

THE LEARNER Live Stream

LED DISPLAY INTERFACE USING EMU8086

LED DISPLAY INTERFACE USING EMU8086

NUMBER OF POSITIVE & NEGATIVE NUMBERS IN A GIVEN ARRAY

NUMBER OF POSITIVE & NEGATIVE NUMBERS IN A GIVEN ARRAY

LENGTH OF A STRING USING EMU8086

LENGTH OF A STRING USING EMU8086

ASCENDING ORDER USING EMU 8086

ASCENDING ORDER USING EMU 8086

SUM OF 'N' NUMBERS USING EMU8086

SUM OF 'N' NUMBERS USING EMU8086

BASIC ARITHMETIC OPERATION IN 8086 USING EMU8086

BASIC ARITHMETIC OPERATION IN 8086 USING EMU8086

LOGICAL OPERATION FOR SETTING & MASKING BITS IN EMULATOR 8086

LOGICAL OPERATION FOR SETTING & MASKING BITS IN EMULATOR 8086

INTRODUCTION TO EMU8086 WITH BASIC ADDITION

INTRODUCTION TO EMU8086 WITH BASIC ADDITION

DESIGN OF BASIC GATES USING COMPLEMENTARY PASS TRANSISTOR LOGIC

DESIGN OF BASIC GATES USING COMPLEMENTARY PASS TRANSISTOR LOGIC

DESIGN OF BASIC GATES USING DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC

DESIGN OF BASIC GATES USING DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC

STATIC CIRCUIT DESIGN FOR COMPLEX LOGIC FUNCTION

STATIC CIRCUIT DESIGN FOR COMPLEX LOGIC FUNCTION

PSEUDO NMOS INVERTER IN LTSPICE

PSEUDO NMOS INVERTER IN LTSPICE

INTRODUCTION TO LTSPICE SOFTWARE WITH CMOS INVERTER CIRCUIT SIMULATION

INTRODUCTION TO LTSPICE SOFTWARE WITH CMOS INVERTER CIRCUIT SIMULATION

DESIGN OF ROM IN VERILOG

DESIGN OF ROM IN VERILOG

DESIGN OF RAM USING VERILOG

DESIGN OF RAM USING VERILOG

WALLACE TREE MULTIPLIER IN VERILOG

WALLACE TREE MULTIPLIER IN VERILOG

BRAUN ARRAY MULTIPLIER IN VERILOG

BRAUN ARRAY MULTIPLIER IN VERILOG

FSM - SEQUENCE DETECTOR IN VERILOG

FSM - SEQUENCE DETECTOR IN VERILOG

CARRY SKIP ADDER IN VERILOG

CARRY SKIP ADDER IN VERILOG

CARRY LOOK AHEAD ADDER IN VERILOG

CARRY LOOK AHEAD ADDER IN VERILOG

SERIAL IN SERIAL OUT SHIFT REGISTER USING BEHAVIORAL MODELING IN VERILOG

SERIAL IN SERIAL OUT SHIFT REGISTER USING BEHAVIORAL MODELING IN VERILOG

SWITCH LEVEL MODELING - CMOS INVERTER, NAND GATE

SWITCH LEVEL MODELING - CMOS INVERTER, NAND GATE

UP-DOWN COUNTER, MOD N COUNTER IN VERILOG USING BEHAVIORAL MODELLING

UP-DOWN COUNTER, MOD N COUNTER IN VERILOG USING BEHAVIORAL MODELLING

T FLIP FLOP USING CASE STATEMENT IN VERILOG

T FLIP FLOP USING CASE STATEMENT IN VERILOG

D FLIP FLOP USING IF ELSE STATEMENT IN VERILOG

D FLIP FLOP USING IF ELSE STATEMENT IN VERILOG

JK FLIP FLOP USING DATAFLOW MODELING IN VERILOG

JK FLIP FLOP USING DATAFLOW MODELING IN VERILOG

SR FLIP FLOP USING GATE LEVEL MODELING IN VERILOG LANGUAGE

SR FLIP FLOP USING GATE LEVEL MODELING IN VERILOG LANGUAGE

4 BIT RIPPLE CARRY ADDER USING FULLADDER IN VERILOG USING XILINX

4 BIT RIPPLE CARRY ADDER USING FULLADDER IN VERILOG USING XILINX

FULL ADDER USING HALF ADDER IN VERILOG

FULL ADDER USING HALF ADDER IN VERILOG

INTRODUCTION to XILINX WITH MODEL SIM SIMULATOR- HALF ADDER

INTRODUCTION to XILINX WITH MODEL SIM SIMULATOR- HALF ADDER

8051 TIMER PROGRAMMING ( SQUARE WAVE GENERATION)

8051 TIMER PROGRAMMING ( SQUARE WAVE GENERATION)

8051 TIMER PROGRAMMING (MODE 1)

8051 TIMER PROGRAMMING (MODE 1)

SERIAL COMMUNICATION INTERFACE WITH 8051

SERIAL COMMUNICATION INTERFACE WITH 8051

DAC INTERFACE (SQUARE, TRIANGLE WAVE GENERATION ) WITH 8051 IN EDSIM51

DAC INTERFACE (SQUARE, TRIANGLE WAVE GENERATION ) WITH 8051 IN EDSIM51

HEXADECIMAL TO BCD IN 8051 USING EDSIM51

HEXADECIMAL TO BCD IN 8051 USING EDSIM51

BCD TO HEXADECIMAL IN 8051 USING EDSIM51

BCD TO HEXADECIMAL IN 8051 USING EDSIM51

SEMICONDUCTOR MEMORY INTERFACING 8086

SEMICONDUCTOR MEMORY INTERFACING 8086

BASIC PROGRAM IN EDSIM 51 TOOL USING DIRECT ADDRESSING

BASIC PROGRAM IN EDSIM 51 TOOL USING DIRECT ADDRESSING

8051 ADDITION USING EDSIM51

8051 ADDITION USING EDSIM51

STEPPER MOTOR INTERFACING WITH EMU 8086

STEPPER MOTOR INTERFACING WITH EMU 8086

WAVE EQUATION FOR STEP INDEX FIBER

WAVE EQUATION FOR STEP INDEX FIBER

WAVE EQN FOR CIRCULAR WAVE GUIDES PART 2

WAVE EQN FOR CIRCULAR WAVE GUIDES PART 2

WAVE EQUATION FOR CIRCULAR WAVE GUIDES PART 1

WAVE EQUATION FOR CIRCULAR WAVE GUIDES PART 1