Канал: MICRO Symposium

MICRO 2023 B. Ramakrishna Rau Award Talk: Joel Emer

MICRO 2023 B. Ramakrishna Rau Award Talk: Joel Emer

MICRO 2023 Keynote 2: Debbie Marr

MICRO 2023 Keynote 2: Debbie Marr

MICRO 2023 Keynote 3: Mark Horowitz

MICRO 2023 Keynote 3: Mark Horowitz

MICRO 2023 Keynote 1: Amin Vahdat

MICRO 2023 Keynote 1: Amin Vahdat

MICRO 2021: ACM Student Research Competition Final Round

MICRO 2021: ACM Student Research Competition Final Round

AHS: An Agile Framework for Hardware Specialization and Software Mapping

AHS: An Agile Framework for Hardware Specialization and Software Mapping

AI Security: New Architectural Horizons in AI Hardware Security

AI Security: New Architectural Horizons in AI Hardware Security

Cloud@MICRO 2021

Cloud@MICRO 2021

Workshop on Architecture, Compiler, and System Support for Multi-Model DNN Workloads

Workshop on Architecture, Compiler, and System Support for Multi-Model DNN Workloads

FireSim / Chipyard: Tutorial on End-to-End Architecture Research Platform

FireSim / Chipyard: Tutorial on End-to-End Architecture Research Platform

HASP 2021: Hardware and Architectural Support for Security and Privacy

HASP 2021: Hardware and Architectural Support for Security and Privacy

NoCArc 2021: 14th International Workshop on Network on Chip Architectures

NoCArc 2021: 14th International Workshop on Network on Chip Architectures

PrecisionHealth: Computational Challenges in Precision Health

PrecisionHealth: Computational Challenges in Precision Health

Vortex: Open-Source RISC-V Based GPGPU

Vortex: Open-Source RISC-V Based GPGPU

MICRO 2021 Opening Remarks

MICRO 2021 Opening Remarks

MICRO 2021 Keynote 1: Michael T. Clark

MICRO 2021 Keynote 1: Michael T. Clark

MICRO 2021 Panel: Microarchitecture Research: The View from the Globe

MICRO 2021 Panel: Microarchitecture Research: The View from the Globe

MICRO 2021 Awards Ceremony

MICRO 2021 Awards Ceremony

MICRO 2021 Keynote 3: Sean Lie

MICRO 2021 Keynote 3: Sean Lie

MICRO 2021 Keynote 2: Anastasia Ailamaki

MICRO 2021 Keynote 2: Anastasia Ailamaki

Invitation to Participate in MICRO 2020

Invitation to Participate in MICRO 2020

MICRO 2020 Opening Remarks

MICRO 2020 Opening Remarks

Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory

Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory

Systematic Crosstalk Mitigation for Superconducting Qubits via Frequency-Aware Compilation

Systematic Crosstalk Mitigation for Superconducting Qubits via Frequency-Aware Compilation

Locality-Centric Data and Threadblock Management for Massive GPUs

Locality-Centric Data and Threadblock Management for Massive GPUs

Deterministic Atomic Buffering

Deterministic Atomic Buffering

CHiRP: Control-Flow History Reuse Prediction

CHiRP: Control-Flow History Reuse Prediction

Jumanji: The Case for Dynamic NUCA in the Datacenter

Jumanji: The Case for Dynamic NUCA in the Datacenter

SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices

SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices

Predicting Execution Times With Partial Simulations in Virtual Memory Research: Why and How

Predicting Execution Times With Partial Simulations in Virtual Memory Research: Why and How

PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron

PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron

Pipette: Improving Core Utilization on Irregular Apps through Intra-Core Pipeline Parallelism

Pipette: Improving Core Utilization on Irregular Apps through Intra-Core Pipeline Parallelism

Coordinated Priority-Aware Charging of Distributed Batteries in Oversubscribed Data Centers

Coordinated Priority-Aware Charging of Distributed Batteries in Oversubscribed Data Centers

Characterizing and Modeling Non-Volatile Memory Systems

Characterizing and Modeling Non-Volatile Memory Systems

MICRO 2020 Keynote 2: Cristina Silvano

MICRO 2020 Keynote 2: Cristina Silvano

BranchNet: A Convolutional Neural Network to Predict Hard-to-Predict Branches

BranchNet: A Convolutional Neural Network to Predict Hard-to-Predict Branches

MICRO 2020 Keynote 1: Rich Wolski

MICRO 2020 Keynote 1: Rich Wolski

CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture

CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture

Speculative Enforcement of Store Atomicity

Speculative Enforcement of Store Atomicity

DUAL: Acceleration of Clustering Algorithms using Digital-Based Processing In-Memory

DUAL: Acceleration of Clustering Algorithms using Digital-Based Processing In-Memory

CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores

CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores

Selective Replication in Memory-Side GPU Caches

Selective Replication in Memory-Side GPU Caches

AQUOMAN: An Analytic-Query Offloading Machine

AQUOMAN: An Analytic-Query Offloading Machine

GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy Efficient Inference

GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy Efficient Inference

Optimized Quantum Compilation for Near-Term Algorithms with OpenPulse

Optimized Quantum Compilation for Near-Term Algorithms with OpenPulse

TrainBox: An Extreme-Scale NN Training Server Architecture by Systematically Balancing Operations

TrainBox: An Extreme-Scale NN Training Server Architecture by Systematically Balancing Operations

Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks

Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks

Duplo: Lifting Redundant Memory Accesses of Deep Neural Networks for GPU Tensor Cores

Duplo: Lifting Redundant Memory Accesses of Deep Neural Networks for GPU Tensor Cores

MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications

MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications

P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks

P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks

Graphene: Strong yet Lightweight Row Hammer Protection

Graphene: Strong yet Lightweight Row Hammer Protection

I-SPY: Context-Driven Conditional Instruction Prefetching with Coalescing

I-SPY: Context-Driven Conditional Instruction Prefetching with Coalescing

DiffTune: Optimizing CPU Simulator Parameters with Learned Differentiable Surrogates

DiffTune: Optimizing CPU Simulator Parameters with Learned Differentiable Surrogates

MICRO 2020 Keynote 3: Srilatha (Bobbie) Manne

MICRO 2020 Keynote 3: Srilatha (Bobbie) Manne

Procrustes: A Dataflow and Accelerator for Sparse Deep Neural Network Training

Procrustes: A Dataflow and Accelerator for Sparse Deep Neural Network Training

ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning

ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning

VR-DANN: Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration

VR-DANN: Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration

More with Less - Deriving More Translation Rules with Less Training Data for DBTs...

More with Less - Deriving More Translation Rules with Less Training Data for DBTs...

PThammer: Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses

PThammer: Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses

TFE: Energy-Efficient Transferred Filter-Based Engine to Compress and Accelerate CNNs

TFE: Energy-Efficient Transferred Filter-Based Engine to Compress and Accelerate CNNs

Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System

Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System

gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling

gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture

HyperPlane: A Scalable Low-Latency Notification Accelerator for Software Data Planes

HyperPlane: A Scalable Low-Latency Notification Accelerator for Software Data Planes

Hardware-Based Always-On Heap Memory Safety

Hardware-Based Always-On Heap Memory Safety

Mesorasi: Architecture Support for Point Cloud Analytics via Delayed-Aggregation

Mesorasi: Architecture Support for Point Cloud Analytics via Delayed-Aggregation

A Locality-Aware Energy-Efficient Accelerator for Graph Mining Applications

A Locality-Aware Energy-Efficient Accelerator for Graph Mining Applications

GenASM: A High-Perf, Low-Power Approximate String Matching Accel Framework for Genome Sequencing

GenASM: A High-Perf, Low-Power Approximate String Matching Accel Framework for Genome Sequencing

ThymesisFlow: A SW-Defined HW/SW Co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation

ThymesisFlow: A SW-Defined HW/SW Co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation

FReaC Cache: Folded-Logic Reconfigurable Computing in the Last Level Cache

FReaC Cache: Folded-Logic Reconfigurable Computing in the Last Level Cache

DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms

DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms

FIdelity: Efficient Resilience Analysis Framework for Deep Learning Accelerators

FIdelity: Efficient Resilience Analysis Framework for Deep Learning Accelerators

SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space

SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting Data Retention

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting Data Retention

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product

Draco: Architectural and Operating System Support for System Call Security

Draco: Architectural and Operating System Support for System Call Security

BOW: Breathing Operand Windows to Exploit Bypassing in GPUs

BOW: Breathing Operand Windows to Exploit Bypassing in GPUs

PerpLE: Improving the Speed and Effectiveness of Memory Consistency Testing

PerpLE: Improving the Speed and Effectiveness of Memory Consistency Testing

D-SOAP: Dynamic Spatial Orientation Affinity Prediction for Caching in Multi-Orientation Memory Syst

D-SOAP: Dynamic Spatial Orientation Affinity Prediction for Caching in Multi-Orientation Memory Syst

Speculation Invariance (InvarSpec): Faster Safe Execution through Program Analysis

Speculation Invariance (InvarSpec): Faster Safe Execution through Program Analysis

CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches

CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches

FlexWatts: A Power- and Workload-Aware Hybrid PDN for Energy-Efficient Microprocessors

FlexWatts: A Power- and Workload-Aware Hybrid PDN for Energy-Efficient Microprocessors

A Benchmarking Framework for Interactive 3D Applications in the Cloud

A Benchmarking Framework for Interactive 3D Applications in the Cloud

Printed Machine Learning Classifiers

Printed Machine Learning Classifiers

Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration

Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration

NCPU: Embedded Neural Arch on Resource-Constrained Low Power Devices for Real-Time End-to-End Perf

NCPU: Embedded Neural Arch on Resource-Constrained Low Power Devices for Real-Time End-to-End Perf

MDM: The GPU Memory Divergence Model

MDM: The GPU Memory Divergence Model

AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing

AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing

RnR: A Software-Assisted Record-and-Replay Hardware Prefetcher

RnR: A Software-Assisted Record-and-Replay Hardware Prefetcher

Building the Computing System for Autonomous Micromobility Vehicles

Building the Computing System for Autonomous Micromobility Vehicles

Fast-BCNN: Massive Neuron Skipping in Bayesian Convolutional Neural Networks

Fast-BCNN: Massive Neuron Skipping in Bayesian Convolutional Neural Networks

SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs

SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs

FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching

FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching

AutoScale: Energy Efficiency Optimization for Stochastic Edge Inference Using Reinforcement Learning

AutoScale: Energy Efficiency Optimization for Stochastic Edge Inference Using Reinforcement Learning

Gemini: Learning to Manage CPU Power for Latency-Critical Search Engines

Gemini: Learning to Manage CPU Power for Latency-Critical Search Engines

Boosting Store Buffer Efficiency with Store-Prefetch Bursts

Boosting Store Buffer Efficiency with Store-Prefetch Bursts

(Almost) Fence-Less Persist Ordering

(Almost) Fence-Less Persist Ordering

Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks

Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks

Newton: A DRAM-Maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning

Newton: A DRAM-Maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning

Ptolemy: Architecture Support for Robust Deep Learning

Ptolemy: Architecture Support for Robust Deep Learning

Improving the Utilization of Micro-Operation Caches in x86 Processors

Improving the Utilization of Micro-Operation Caches in x86 Processors

Optimizing the Memory Hierarchy by Compositing Automatic Transformations on Computations and Data

Optimizing the Memory Hierarchy by Compositing Automatic Transformations on Computations and Data

TensorDash: Exploiting Sparsity to Accelerate Deep Neural Network Training

TensorDash: Exploiting Sparsity to Accelerate Deep Neural Network Training

MICRO 2020 Awards Ceremony

MICRO 2020 Awards Ceremony

Circuit Compilation Methodologies for Quantum Approximate Optimization Algorithm

Circuit Compilation Methodologies for Quantum Approximate Optimization Algorithm

GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing

GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing

Virtualized Logical Qubits: A 2.5D Architecture for Error-Corrected Quantum Computing

Virtualized Logical Qubits: A 2.5D Architecture for Error-Corrected Quantum Computing

Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash

Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash