Канал: MUHAMMAD SHAKEEL AKRAM

Ta'uz, Tasmia, & Dua For Meal

Ta'uz, Tasmia, & Dua For Meal

COUNTING 1-20 By Abdur Rahman Bin Shakeel

COUNTING 1-20 By Abdur Rahman Bin Shakeel

Stand Alone Smart Devices Enabled with AI Cardiac Diagnosis #cardiology #ai #smartgadgets

Stand Alone Smart Devices Enabled with AI Cardiac Diagnosis #cardiology #ai #smartgadgets

Reason of High Mortalities Due To Cardiac Diseases #cardiology #education

Reason of High Mortalities Due To Cardiac Diseases #cardiology #education

Arrhythmia: A Real Trouble Maker in Cardiac Diseases

Arrhythmia: A Real Trouble Maker in Cardiac Diseases

50M of Us @ Risk Due To Cardiac Diseases. 37% of All Deaths.

50M of Us @ Risk Due To Cardiac Diseases. 37% of All Deaths.

How Many Senses Do We Have? Five Senses

How Many Senses Do We Have? Five Senses

Ulster University | Doctoral College | 3MT Initial Heats |Cardiac Diseases AI Diagnostics

Ulster University | Doctoral College | 3MT Initial Heats |Cardiac Diseases AI Diagnostics

آ ا ب | Urdu Ka Guldasta | Third Edition | By Gulab | Oxford

آ ا ب | Urdu Ka Guldasta | Third Edition | By Gulab | Oxford

XILINX/FINN AssertionError: MultiThreshold_3: Signed output requres actval less than 0

XILINX/FINN AssertionError: MultiThreshold_3: Signed output requres actval less than 0

"Introduce Yourself"

"Introduce Yourself"

The Toys' Story | ORT Stories Stage 2 | by Alex Brychta and Roderick Hunt | Oxford

The Toys' Story | ORT Stories Stage 2 | by Alex Brychta and Roderick Hunt | Oxford

Xilinx Vivado and ZCU102 FPGA Program ERROR: [Labtools 27-3165] End of startup status: LOW

Xilinx Vivado and ZCU102 FPGA Program ERROR: [Labtools 27-3165] End of startup status: LOW

CRITICAL WARNING: [Labtools 27-3421] xczu9_0 PL Power Status OFF, cannot connect PL TAP. Check POR_B

CRITICAL WARNING: [Labtools 27-3421] xczu9_0 PL Power Status OFF, cannot connect PL TAP. Check POR_B

Xilinx Vivado: Device Constraints Tab is Missing in Synthesized Design Window

Xilinx Vivado: Device Constraints Tab is Missing in Synthesized Design Window

FPGA (ZCU102) Vivado Complete Tutorial & Basic Error Solution

FPGA (ZCU102) Vivado Complete Tutorial & Basic Error Solution

ssh-keygen issue

ssh-keygen issue

No user exists for uid 1000 for I have no name!@finn_dev_username$

No user exists for uid 1000 for I have no name!@finn_dev_username$

ECD LAB13 VI Characteristics curve of TRIAC using Multisim

ECD LAB13 VI Characteristics curve of TRIAC using Multisim

Home Made PCB of Variable Power Supply, MP3 player with Bluetooth, and voice over Bluetooth.

Home Made PCB of Variable Power Supply, MP3 player with Bluetooth, and voice over Bluetooth.

DLD LAB8 FPGA's Slice (LUTs) & IOBs Used by Module in Xilinx. (View/Edit Routed Design FPGA Editor)

DLD LAB8 FPGA's Slice (LUTs) & IOBs Used by Module in Xilinx. (View/Edit Routed Design FPGA Editor)

DLD LABp2 2-bit Half Adder, 2-bit &4-bit Full Adder, and 2-bit Half Subtractor design using Xilinx.

DLD LABp2 2-bit Half Adder, 2-bit &4-bit Full Adder, and 2-bit Half Subtractor design using Xilinx.

ECD LAB6 MOSFET Digital Switching (Logic Gates (XOR etc.) Implementation using CMOS) using Multisim

ECD LAB6 MOSFET Digital Switching (Logic Gates (XOR etc.) Implementation using CMOS) using Multisim

ECD LEC13 MOSFET Digital Switching (Class D Power Amplifier)

ECD LEC13 MOSFET Digital Switching (Class D Power Amplifier)

ECD LEC12 MOSFET Digital Switching (CMOS Design)

ECD LEC12 MOSFET Digital Switching (CMOS Design)

DLD LAB7 Logic Gates Implementation and Synthesis using Xilinx ISE 14.7

DLD LAB7 Logic Gates Implementation and Synthesis using Xilinx ISE 14.7

DLD LAB7p2 Schematic Designing in Xilinx

DLD LAB7p2 Schematic Designing in Xilinx

DLD_LEC8_Comarator Equality and Inequality, Encoder, Decimal to BCD Encoder, Decoder(BCD to 7 Seg)

DLD_LEC8_Comarator Equality and Inequality, Encoder, Decimal to BCD Encoder, Decoder(BCD to 7 Seg)

ECD LAB5_DMOSFET Common Source Amplifier in (Depletion, Enhancement, saturation mode) using Multisim

ECD LAB5_DMOSFET Common Source Amplifier in (Depletion, Enhancement, saturation mode) using Multisim

ECD LEC11 MOSFET Analog Switching (Mulitplexer, Sampling etc)

ECD LEC11 MOSFET Analog Switching (Mulitplexer, Sampling etc)

ECD LEC10 JFET, DMOSFET & EMOSFET Common Gate, Common Drain and Casecode Amplifier

ECD LEC10 JFET, DMOSFET & EMOSFET Common Gate, Common Drain and Casecode Amplifier

ECD LEC9 D & E MOSFET Zero Bias & Voltage Divider Bias Common Source Amplifier

ECD LEC9 D & E MOSFET Zero Bias & Voltage Divider Bias Common Source Amplifier

DLD LAB6 Designing Full Adder, and Parallel Adders using Multisim

DLD LAB6 Designing Full Adder, and Parallel Adders using Multisim

How to Extend the Length and Hight of Multisim's Workspace

How to Extend the Length and Hight of Multisim's Workspace

DLD LAB6p2 Designing 4 bit,32-bit, and N-bit Parallel Adder using Multisim

DLD LAB6p2 Designing 4 bit,32-bit, and N-bit Parallel Adder using Multisim

DLD LEC7 Implementing Combinational Logic using SOP (Truth table to Schematic) and POS

DLD LEC7 Implementing Combinational Logic using SOP (Truth table to Schematic) and POS

DLD LEC8 Implementing Scenario Combinational Logic using Universal NOR and NAND gate

DLD LEC8 Implementing Scenario Combinational Logic using Universal NOR and NAND gate

ECD LEC8 JFET Common Source Amplifier Working and Analysis

ECD LEC8 JFET Common Source Amplifier Working and Analysis

ECD LEC7 FET amplifiers and switching circuit's introduction and DC&AC analysis combined graph

ECD LEC7 FET amplifiers and switching circuit's introduction and DC&AC analysis combined graph

ECD LAB4 Design and Analysis of JFET Common Source Amplifier using Multism

ECD LAB4 Design and Analysis of JFET Common Source Amplifier using Multism

DLD LAB5 Understanding and Implementation of Half Adder and Half Subtractor using MULTISIM

DLD LAB5 Understanding and Implementation of Half Adder and Half Subtractor using MULTISIM

DLD LEC6 Sum of Product SOP and Product of Sum POS Understanding

DLD LEC6 Sum of Product SOP and Product of Sum POS Understanding

DLD LEC7 Karnaugh MAP K MAP Understanding and SOP, POS simplification using K MAP

DLD LEC7 Karnaugh MAP K MAP Understanding and SOP, POS simplification using K MAP

ECD LAB3p2 DMOSFET and EMOSFET Transfer Characteristics Curve using DC Sweep on Multisim

ECD LAB3p2 DMOSFET and EMOSFET Transfer Characteristics Curve using DC Sweep on Multisim

ECD LAB3 DMOSFET and EMOSFET Transfer Characteristics Curve and different Biasing using Multisim

ECD LAB3 DMOSFET and EMOSFET Transfer Characteristics Curve and different Biasing using Multisim

DLD LAB4 P2 2input XNOR gate implementation using 745LS266, 4077BP in Multisim

DLD LAB4 P2 2input XNOR gate implementation using 745LS266, 4077BP in Multisim

DLD LAB4 2input XOR(74ls86) and XNOR(266) gate implementation for multiple inputs using Multisim

DLD LAB4 2input XOR(74ls86) and XNOR(266) gate implementation for multiple inputs using Multisim

ECD LEC6 Power MOSFETs Like U, V, LT etc

ECD LEC6 Power MOSFETs Like U, V, LT etc

ECD LEC5 E MOSFET Voltage Divider and Drain Feedback Biasing

ECD LEC5 E MOSFET Voltage Divider and Drain Feedback Biasing

DLD LEC5 Boolean Algebra Laws and Rules

DLD LEC5 Boolean Algebra Laws and Rules

DLD LEC4 Signle Precision Floating Point Binary, Even, Odd, and CRC Error Detection Techniques

DLD LEC4 Signle Precision Floating Point Binary, Even, Odd, and CRC Error Detection Techniques

How to Add Digital Signature in PDF File using Adobe Acrobat Reader

How to Add Digital Signature in PDF File using Adobe Acrobat Reader

ECD LAB2 JFET Biasing Self Bias and Voltage Divider Bias

ECD LAB2 JFET Biasing Self Bias and Voltage Divider Bias

DLD LAB3 2input NAND and NOR gate implementation for multiple inputs using Multisim

DLD LAB3 2input NAND and NOR gate implementation for multiple inputs using Multisim

ECD LEC4 D MOSFET and E MOSFET Working and D MOSFET Zero Biasing

ECD LEC4 D MOSFET and E MOSFET Working and D MOSFET Zero Biasing

ECD LEC3 JFET Voltage Divider Biasing & Current Source Biasing

ECD LEC3 JFET Voltage Divider Biasing & Current Source Biasing

DLD LEC3 Signed Number and its Arithmatic

DLD LEC3 Signed Number and its Arithmatic

DLD LEC2 Binary Arithmatic

DLD LEC2 Binary Arithmatic

ECD LAB1 JFET Transfer Charecteristics Curve using Multisim

ECD LAB1 JFET Transfer Charecteristics Curve using Multisim

DLD LAB2 2Input OR Gate and NOT gate for multiple input and combinational circuit using Multisim

DLD LAB2 2Input OR Gate and NOT gate for multiple input and combinational circuit using Multisim

ECD LEC2 JFET Transconductance and Self Biasing

ECD LEC2 JFET Transconductance and Self Biasing

DLD LEC1 Number Systems and Their Interconversions

DLD LEC1 Number Systems and Their Interconversions

DLD LAB1 2 Input AND Gate Implementation for multiple inputs More than 2 using Multisim mp4

DLD LAB1 2 Input AND Gate Implementation for multiple inputs More than 2 using Multisim mp4

ECD LEC1 JFET Characteristics And Parameters

ECD LEC1 JFET Characteristics And Parameters

LAB9 BJT Biasings using multisim by Engr Naqeeb

LAB9 BJT Biasings using multisim by Engr Naqeeb

LAB8 VI Characteristics Curve of Zener Diode using Multisim by Engr Naqeeb

LAB8 VI Characteristics Curve of Zener Diode using Multisim by Engr Naqeeb

LAB7 Diode Clamper Circuits using Multisim by Engr Naqeeb

LAB7 Diode Clamper Circuits using Multisim by Engr Naqeeb

LAB6 Diode Clipper Circuits using multisim by Engr Naqeeb

LAB6 Diode Clipper Circuits using multisim by Engr Naqeeb

LAB5 Full Wave Rectification using multisim by Engr Naqeeb

LAB5 Full Wave Rectification using multisim by Engr Naqeeb

LAB4 Half wave rectification using multism by Engr Naqeeb

LAB4 Half wave rectification using multism by Engr Naqeeb

LAB3 Diode VI Characteristics Curve using multisim by Engr Naqeeb

LAB3 Diode VI Characteristics Curve using multisim by Engr Naqeeb

LAB2 Function Generator and Oscilloscope in Multisim by Engr Naqeeb

LAB2 Function Generator and Oscilloscope in Multisim by Engr Naqeeb

LAB1 Introduction to Multisim, Proteous, & Pspice the electronic circuit simulators by Engr Naqeeb

LAB1 Introduction to Multisim, Proteous, & Pspice the electronic circuit simulators by Engr Naqeeb

LAB Common Emitter Amplifier Simulation using Multisim

LAB Common Emitter Amplifier Simulation using Multisim

LEC13 Commn Collector and Common Base Amplifier

LEC13 Commn Collector and Common Base Amplifier

LEC14 Darlington Pair

LEC14 Darlington Pair

LEC12 Common Emitter Amplifiers

LEC12 Common Emitter Amplifiers

LEC11 BJT Amplifiers

LEC11 BJT Amplifiers

LEC10 BJT Bias Circuits

LEC10 BJT Bias Circuits

LEC9 BJT and its Biasings

LEC9 BJT and its Biasings

LEC8 Introduction to Bipolar Junction Transistor

LEC8 Introduction to Bipolar Junction Transistor

LEC7 Special Purpose Diodes

LEC7 Special Purpose Diodes

LEC6 Inroduction to Zener Diode Part2

LEC6 Inroduction to Zener Diode Part2

LEC6 Inroduction to Zener Diode Part1

LEC6 Inroduction to Zener Diode Part1

LEC5 Clipper and Clampers

LEC5 Clipper and Clampers

LEC4 Bridge Full Wave Rectification with filter and regulator

LEC4 Bridge Full Wave Rectification with filter and regulator

LEC3 Half and Full Wave Rectification

LEC3 Half and Full Wave Rectification

LEC2 Introduction to Diode

LEC2 Introduction to Diode

LEC1 Introduction to Semiconductors

LEC1 Introduction to Semiconductors

Hanzla's Engineering

Hanzla's Engineering

Please ensure that this file is available in the current working directory. Vivado Error

Please ensure that this file is available in the current working directory. Vivado Error

JFET Characteristics Curve using NI Multisim P2

JFET Characteristics Curve using NI Multisim P2

JFET Characteristics Curve using NI Multisim P1

JFET Characteristics Curve using NI Multisim P1

Xilinx Simulation Tutorial Part1

Xilinx Simulation Tutorial Part1

Xilinx Simulation Tutorial Part2

Xilinx Simulation Tutorial Part2

Multisim Simulation Tutorial

Multisim Simulation Tutorial

Xilinx Modelsim Simulation Tutorial

Xilinx Modelsim Simulation Tutorial