Канал: Engineers Learning Hub - Dr. Irfan Ahmad Pindoo

Fundamentals of Semiconductor Devices || Revision Series || Part-02

Fundamentals of Semiconductor Devices || Revision Series || Part-02

Fundamentals of Semiconductor Devices || Revision Series || Part-01

Fundamentals of Semiconductor Devices || Revision Series || Part-01

Fundamentals of D.C and A.C. Circuits || Revision Series || Part-02

Fundamentals of D.C and A.C. Circuits || Revision Series || Part-02

Fundamentals of D.C. and A.C Circuits || Revision Series || Part-01

Fundamentals of D.C. and A.C Circuits || Revision Series || Part-01

Carry Look Ahead Adder| 4-Bits | 17 | Combinational Circuits | Digital Electronics

Carry Look Ahead Adder| 4-Bits | 17 | Combinational Circuits | Digital Electronics

Ripple Carry Adder| 4-Bits | 16 | Combinational Circuits | Digital Electronics

Ripple Carry Adder| 4-Bits | 16 | Combinational Circuits | Digital Electronics

Realization of Full Subtractor using NAND gates only |15|Combinational Circuits| Digital Electronics

Realization of Full Subtractor using NAND gates only |15|Combinational Circuits| Digital Electronics

Realization of Half Subtractor using NOR gates only |14| Combinational Circuits |Digital Electronics

Realization of Half Subtractor using NOR gates only |14| Combinational Circuits |Digital Electronics

Realization of Half Subtractor using NAND gates only |13|Combinational Circuits |Digital Electronics

Realization of Half Subtractor using NAND gates only |13|Combinational Circuits |Digital Electronics

Realization of Full Adder using NAND gates only | 12 | Combinational Circuits | Digital Electronics

Realization of Full Adder using NAND gates only | 12 | Combinational Circuits | Digital Electronics

Realization of Half Adder using NOR gates only | 11 | Combinational Circuits | Digital Electronics

Realization of Half Adder using NOR gates only | 11 | Combinational Circuits | Digital Electronics

Realization of Half Adder using NAND gates only || 10 ||Combinational Circuits | Digital Electronics

Realization of Half Adder using NAND gates only || 10 ||Combinational Circuits | Digital Electronics

Implementation of Full Subtractor using Half Subtractors || 09 || Combinational Circuits

Implementation of Full Subtractor using Half Subtractors || 09 || Combinational Circuits

Full Subtractor || 08 || Combinational Logic Circuits || Digital Electronics

Full Subtractor || 08 || Combinational Logic Circuits || Digital Electronics

Half subtractor || 07 || Combinational Logic Circuits

Half subtractor || 07 || Combinational Logic Circuits

Implementation of Full Adder using Half Adders || 06|| Combinational Logic Circuits

Implementation of Full Adder using Half Adders || 06|| Combinational Logic Circuits

Full Adder || 05 || Digital Electronics

Full Adder || 05 || Digital Electronics

Half Adder || 04 || Digital Electronics

Half Adder || 04 || Digital Electronics

BCD to Excess-3 Code Conversion using Design Procedure Steps || 03 || Digital Electronics

BCD to Excess-3 Code Conversion using Design Procedure Steps || 03 || Digital Electronics

Design Procedure of Combinational Circuits || 02 || Digital Electronics

Design Procedure of Combinational Circuits || 02 || Digital Electronics

Introduction to Combinational Logic Circuits || 01 || Digital Electronics

Introduction to Combinational Logic Circuits || 01 || Digital Electronics

Video # 5 | Digital Electronics | Number System | Ques 5 | Solved GATE problem.

Video # 5 | Digital Electronics | Number System | Ques 5 | Solved GATE problem.

Video # 4 | Digital Electronics | Number System | Ques 4 | Solved GATE Problem.

Video # 4 | Digital Electronics | Number System | Ques 4 | Solved GATE Problem.

Digital Electronics | Number System | Hexadecimal and BCD code | Question 3

Digital Electronics | Number System | Hexadecimal and BCD code | Question 3

Video 2 | Digital Electronics | Solved GATE / IES / PSUs Questions | ECE, CSE, EE, and IN branches

Video 2 | Digital Electronics | Solved GATE / IES / PSUs Questions | ECE, CSE, EE, and IN branches

Digital Electronics || Solved GATE / IES / PSUs Questions || for branches ECE, CSE, EE and IN.

Digital Electronics || Solved GATE / IES / PSUs Questions || for branches ECE, CSE, EE and IN.

Quick Revision of Transformers and Motors (Unit 3: ECE 131)

Quick Revision of Transformers and Motors (Unit 3: ECE 131)

Quick Revision of AC Fundamentals

Quick Revision of AC Fundamentals

Numericals Based on Dependent Energy Sources || Superposition Theorem

Numericals Based on Dependent Energy Sources || Superposition Theorem

Use of Scientific Calculators for AC Circuit Analysis || Using a FREE app || Android Version

Use of Scientific Calculators for AC Circuit Analysis || Using a FREE app || Android Version

Numericals based on Dependent Energy Sources || Nodal Analysis || Mesh Analysis

Numericals based on Dependent Energy Sources || Nodal Analysis || Mesh Analysis

Coursera | Interfacing with the Arduino | Week 2 | Graded Assignment

Coursera | Interfacing with the Arduino | Week 2 | Graded Assignment

Coursera | Interfacing with the Arduino | Week 1 | Graded Assignment

Coursera | Interfacing with the Arduino | Week 1 | Graded Assignment

Programmable Array Logic (PAL) || Introduction || Construction || Programming

Programmable Array Logic (PAL) || Introduction || Construction || Programming

Programmable Logic Array(PLA) || Introduction || Construction || Programming

Programmable Logic Array(PLA) || Introduction || Construction || Programming

Tutorial Problems on Counter Design || (PART 3)

Tutorial Problems on Counter Design || (PART 3)

Programmable Read Only Memory (PROM) || Introduction || Construction || Programming

Programmable Read Only Memory (PROM) || Introduction || Construction || Programming

Introduction to Programmable Logic Devices (PLDs) || Types of PLDs || PROM, PAL and PLA ||

Introduction to Programmable Logic Devices (PLDs) || Types of PLDs || PROM, PAL and PLA ||

DRAM || Read, Write and Hold Operation || Concept of Refresh Cycles in DRAM

DRAM || Read, Write and Hold Operation || Concept of Refresh Cycles in DRAM

SRAM || Write Operation || Differences Between 6T Cell vs 4T Cell Design

SRAM || Write Operation || Differences Between 6T Cell vs 4T Cell Design

SRAM || Read Operation || Hold Operation || Using 6T Cell Design

SRAM || Read Operation || Hold Operation || Using 6T Cell Design

Introduction to Computer Memory || (Part-2) || RAM vs ROM || SRAM vs DRAM | Types of ROM

Introduction to Computer Memory || (Part-2) || RAM vs ROM || SRAM vs DRAM | Types of ROM

Synchronous Counters | Introduction and Design Procedure | (PART 2)

Synchronous Counters | Introduction and Design Procedure | (PART 2)

Introduction to Computer Memory | (Part-1) | Differences between Primary and Secondary Memory |

Introduction to Computer Memory | (Part-1) | Differences between Primary and Secondary Memory |

Tutorial Problems (Part-2): Design of Asynchronous Mod-6 UP Counter using T flip flop

Tutorial Problems (Part-2): Design of Asynchronous Mod-6 UP Counter using T flip flop

Tutorial Problems (Part-1): Mod-8 Synchronous Down Counter using JK Flip Flop

Tutorial Problems (Part-1): Mod-8 Synchronous Down Counter using JK Flip Flop

Johnson's Counter(Shift Register Counter)

Johnson's Counter(Shift Register Counter)

RING COUNTER (Shift Register Counter) and its Applications

RING COUNTER (Shift Register Counter) and its Applications

Parallel In Serial Out (PISO) Shift Register

Parallel In Serial Out (PISO) Shift Register

Parallel In Parallel Out (PIPO) Shift Register

Parallel In Parallel Out (PIPO) Shift Register

Serial In Parallel Out (SIPO) Shift Register

Serial In Parallel Out (SIPO) Shift Register

Serial In Serial Out (SISO) Shift Register

Serial In Serial Out (SISO) Shift Register

Register and its Types: An Introduction

Register and its Types: An Introduction

PROTEUS DEMONSTRATION: Visualize the output of Decade Counter on 7 segment Display ((Part 2)

PROTEUS DEMONSTRATION: Visualize the output of Decade Counter on 7 segment Display ((Part 2)

Practical: Visualize the output of Decade Counter on 7 segment Display (Design Connections: Part 1)

Practical: Visualize the output of Decade Counter on 7 segment Display (Design Connections: Part 1)

Design of 3 Bit Synchronous UP Counter using JK Flip-Flop (Part-2)

Design of 3 Bit Synchronous UP Counter using JK Flip-Flop (Part-2)

Design of 3 Bit Synchronous UP Counter using JK Flip-Flop (Part-1)

Design of 3 Bit Synchronous UP Counter using JK Flip-Flop (Part-1)

Synchronous Counters | Introduction and Design Procedure | (PART 1)

Synchronous Counters | Introduction and Design Procedure | (PART 1)

Design of Asynchronous Decade Counter

Design of Asynchronous Decade Counter

Design of Asynchronous Up-Down Counter

Design of Asynchronous Up-Down Counter

Design of 3-bit Asynchronous Binary Down Counter

Design of 3-bit Asynchronous Binary Down Counter

Design of 2-bit Asynchronous Down Counter

Design of 2-bit Asynchronous Down Counter

Design of 3-bit Asynchronous Binary UP Counter

Design of 3-bit Asynchronous Binary UP Counter

Design of 2-bit Asynchronous Binary UP Counter

Design of 2-bit Asynchronous Binary UP Counter

Introduction to Counters | Types of Counters| Asynchronous vs Synchronous Counter Difference

Introduction to Counters | Types of Counters| Asynchronous vs Synchronous Counter Difference

Proteus Demonstration of Synchronous 3-Bit Binary Counter

Proteus Demonstration of Synchronous 3-Bit Binary Counter

Design of 3 bit Synchronous UP/DOWN Counter

Design of 3 bit Synchronous UP/DOWN Counter

Speed Control of a DC Motor using Proteus Design Suite

Speed Control of a DC Motor using Proteus Design Suite

Norton's Theorem (Part-1) | Detailed Explanation and its Significance in Electrical Engineering

Norton's Theorem (Part-1) | Detailed Explanation and its Significance in Electrical Engineering

Thevenin's Theorem (Part-2) | Solved Example | Mathematical Proof

Thevenin's Theorem (Part-2) | Solved Example | Mathematical Proof

Thevenin's Theorem (Part-1) | Detailed Explanation and its Significance in Electrical Engineering

Thevenin's Theorem (Part-1) | Detailed Explanation and its Significance in Electrical Engineering

Superposition Theorem | Solved Example

Superposition Theorem | Solved Example

Concept of Linearity in a Superposition Theorem

Concept of Linearity in a Superposition Theorem

Superposition Theorem (Part 2)| Solved Example

Superposition Theorem (Part 2)| Solved Example

Superposition Theorem (Part 1): Concepts Explained

Superposition Theorem (Part 1): Concepts Explained

Nodal Analysis | Solved Example 2 with Dependent Source

Nodal Analysis | Solved Example 2 with Dependent Source

Nodal Analysis | Solved Example with Dependent Source

Nodal Analysis | Solved Example with Dependent Source

Mesh Analysis (Part 2): Solving KVL equations with Cramer's Method

Mesh Analysis (Part 2): Solving KVL equations with Cramer's Method

Mesh Analysis (Part 1): Concept and a Solved Example

Mesh Analysis (Part 1): Concept and a Solved Example

Nodal Analysis (Part 2) and Problem Solving using Cramer's Method

Nodal Analysis (Part 2) and Problem Solving using Cramer's Method

Nodal Analysis (Part 1)| Concept and Problem Solving

Nodal Analysis (Part 1)| Concept and Problem Solving

Wye-Delta Transformation Formulas with Proof

Wye-Delta Transformation Formulas with Proof

Delta Wye Transformation Formulas with Proof (Continued)

Delta Wye Transformation Formulas with Proof (Continued)

Delta-Wye Transformation Formulas with Proof

Delta-Wye Transformation Formulas with Proof