Канал: BOPV

Networks 4.4: Subnets

Networks 4.4: Subnets

Networks 4.3: IP Version 6

Networks 4.3: IP Version 6

Networks 4.2: Internet Protocol

Networks 4.2: Internet Protocol

Networks 4:1 Routers and Switches

Networks 4:1 Routers and Switches

Networks 3.3: Transmission Control Protocol (TCP)

Networks 3.3: Transmission Control Protocol (TCP)

Networks 3.2: Reliable Transport

Networks 3.2: Reliable Transport

Networks 3.1: Transport Layer

Networks 3.1: Transport Layer

Networks 3.4: Congestion Control

Networks 3.4: Congestion Control

Networks 2.4: Socket Programming

Networks 2.4: Socket Programming

Networks 2.3: DNS, Streaming Protocols

Networks 2.3: DNS, Streaming Protocols

Networks 2.1: Application Layer

Networks 2.1: Application Layer

Networks 1.3: Delays, Queueing, Simulations

Networks 1.3: Delays, Queueing, Simulations

Networks 2.2: Application Protocols

Networks 2.2: Application Protocols

Networks 1.2: Circuit Switching, LAN & WAN

Networks 1.2: Circuit Switching, LAN & WAN

Networks 1.1: Introduction to Networking

Networks 1.1: Introduction to Networking

Intro to Embedded Programming

Intro to Embedded Programming

Virutoso-Part 8 Synthesizing Verilog

Virutoso-Part 8 Synthesizing Verilog

Virutoso-Part7 Cell Characterization

Virutoso-Part7 Cell Characterization

Virtuoso-Part 6 Stick Figures, Logic, and Standard Cells

Virtuoso-Part 6 Stick Figures, Logic, and Standard Cells

Virtuoso-Part 5 Standard cell templates

Virtuoso-Part 5 Standard cell templates

Virtuoso - Part4 - Three different types of simulations

Virtuoso - Part4 - Three different types of simulations

Virtuoso - Part3 - Building the Inverter Layout

Virtuoso - Part3 - Building the Inverter Layout

Virtuoso - Part2 - Basic simulation and comparison of parts

Virtuoso - Part2 - Basic simulation and comparison of parts

Virtuoso - Part 1 - Schematic Capture using Virtuoso Layout

Virtuoso - Part 1 - Schematic Capture using Virtuoso Layout

MPLAB X UART & SDCARD Demo - 1/2

MPLAB X UART & SDCARD Demo - 1/2

Yocto Linux #6 - Application Deployment

Yocto Linux #6 - Application Deployment

Yocto Linux #5 - Final kernel driver

Yocto Linux #5 - Final kernel driver

Yocto Linux #4 - Kernel Module read, write, ioctl

Yocto Linux #4 - Kernel Module read, write, ioctl

Yocto Linux #3 - Hello World Kernel Module

Yocto Linux #3 - Hello World Kernel Module

Yocto Linux #2 - QEMU for Zynq System

Yocto Linux #2 - QEMU for Zynq System

Yocto Linux #1 - Initial setup and ZedBoard bring-up

Yocto Linux #1 - Initial setup and ZedBoard bring-up

Vivado-Seven Segment #3

Vivado-Seven Segment #3

Vivado-Seven Seg #2

Vivado-Seven Seg #2

Vivado-Seven Seg #1 part b

Vivado-Seven Seg #1 part b

Vivado Seven Segment Display #1

Vivado Seven Segment Display #1

Vivado Custom IP with Memory Mapped I/O

Vivado Custom IP with Memory Mapped I/O

Vivado ILA Debugging

Vivado ILA Debugging

First project with Vivado

First project with Vivado

OrCAD-Allegro

OrCAD-Allegro

OrCAD Capture

OrCAD Capture

SMD White Wiring a Trace

SMD White Wiring a Trace

LPKF-Milling

LPKF-Milling

LPKF-Electroplating (2/2)

LPKF-Electroplating (2/2)

LPKF-Electroplating (1/2)

LPKF-Electroplating (1/2)

LPKF-Drilling the Board

LPKF-Drilling the Board

Using Eclipse for C

Using Eclipse for C

VMWare, Ubuntu, Eclipse

VMWare, Ubuntu, Eclipse

Intro to Verilog using ISE

Intro to Verilog using ISE

Building EDK projects with core generated modules

Building EDK projects with core generated modules

Xilinx EDK to SDK Demonstration

Xilinx EDK to SDK Demonstration

Xilinx Platform Studio - Setup Base System Builder for XUPV5 Board

Xilinx Platform Studio - Setup Base System Builder for XUPV5 Board

I2C - Bus Master - Step 4

I2C - Bus Master - Step 4

I2C - Bus Master - Step 3

I2C - Bus Master - Step 3

I2C - Bus Master - Step 1

I2C - Bus Master - Step 1

I2C - Bus Master - Step 2

I2C - Bus Master - Step 2

Introduction to Simulating Verilog using Xilinx and isim

Introduction to Simulating Verilog using Xilinx and isim

Gate Modeling with ISE

Gate Modeling with ISE

Xilinx / ISE Assign Package Pins

Xilinx / ISE Assign Package Pins