Канал: Ajay Rupani

Realization the R S, J K, D flip flops and Serial in Parallel out Shift Register on Virtual Lab

Realization the R S, J K, D flip flops and Serial in Parallel out Shift Register on Virtual Lab

Design and Simulation of 8x1 using VHDL on Xilinx ISE Design Suite

Design and Simulation of 8x1 using VHDL on Xilinx ISE Design Suite

Design and Simulation of 2 to 4 Decoder and 8 to 3 Encoder using VHDL on Xilinx ISE Design Suite

Design and Simulation of 2 to 4 Decoder and 8 to 3 Encoder using VHDL on Xilinx ISE Design Suite

Half and full Subtractor, 4x1 Mux and 1x4 Demux on Virtual Lab developed by IIT Roorkee

Half and full Subtractor, 4x1 Mux and 1x4 Demux on Virtual Lab developed by IIT Roorkee

Digital Electronics Lab Practicals on Virtual Lab

Digital Electronics Lab Practicals on Virtual Lab

Design and Simulation all the logic gates using VHDL on Xilinx ISE Design Suite

Design and Simulation all the logic gates using VHDL on Xilinx ISE Design Suite

VHDL Codes of Logic Gates and their implementation using Xilinx

VHDL Codes of Logic Gates and their implementation using Xilinx

VLSI DesignFlow in detail

VLSI DesignFlow in detail

Realization of Decoders

Realization of Decoders

Realization of Half Adder and Full Adder

Realization of Half Adder and Full Adder

SOP and POS

SOP and POS

SOP and POS Expressions

SOP and POS Expressions

Universal Logic Gates

Universal Logic Gates

MUX and DEMUX

MUX and DEMUX

Multiplexers and their applications

Multiplexers and their applications

Multiplexers and Demultiplexers

Multiplexers and Demultiplexers

Multiplexer and Demultiplexer

Multiplexer and Demultiplexer

K Maps for 5 Variables

K Maps for 5 Variables

K Maps Introduction III

K Maps Introduction III

K Maps for POS Part II

K Maps for POS Part II

K Maps for 6 Variables Part II

K Maps for 6 Variables Part II

K Maps for POS Expressions

K Maps for POS Expressions

K maps for 6 variables Part I

K maps for 6 variables Part I

K maps for 4 Variables

K maps for 4 Variables

Introduction to K Maps

Introduction to K Maps

Examples of K Maps

Examples of K Maps

BCD Adder and ALU

BCD Adder and ALU

Difference between Combinational and Sequential Logic Circuits

Difference between Combinational and Sequential Logic Circuits

Cocepts of Boolean Algebra

Cocepts of Boolean Algebra

Code Conversion Part II

Code Conversion Part II

Code Conversion Part I

Code Conversion Part I

K maps Examples

K maps Examples

Boolean Algebra and Logic Gates Part II

Boolean Algebra and Logic Gates Part II

Boolean Algebra and Logic Gates Part I

Boolean Algebra and Logic Gates Part I

Number Systems

Number Systems