Канал: Jairam Gouda

17. 8T SRAM Cell | Integrated Circuit Memory

17. 8T SRAM Cell | Integrated Circuit Memory

16. 7T SRAM Cell | Integrated Circuit Memories

16. 7T SRAM Cell | Integrated Circuit Memories

15. SRAM Cell Stability | Integrated Circuit Memories

15. SRAM Cell Stability | Integrated Circuit Memories

Design Technology Co-optimization (DTCO) | VLSI

Design Technology Co-optimization (DTCO) | VLSI

14. 6T SRAM Cell Write Operation | Integrated Circuit Memory

14. 6T SRAM Cell Write Operation | Integrated Circuit Memory

13. Read Operation of SRAM Cell | Integrated Circuit Memories

13. Read Operation of SRAM Cell | Integrated Circuit Memories

12. Introduction to 6T SRAM cell | Integrated Circuit Memories

12. Introduction to 6T SRAM cell | Integrated Circuit Memories

11. Memory Array Architecture | Integrated Circuit Memory

11. Memory Array Architecture | Integrated Circuit Memory

10. Introduction to DRAM | Integrated Circuit Memory

10. Introduction to DRAM | Integrated Circuit Memory

9. Introduction to SRAM | Integrated Circuit Memory

9. Introduction to SRAM | Integrated Circuit Memory

8. Introduction to Read write memory | Integrated Circuit Memory

8. Introduction to Read write memory | Integrated Circuit Memory

7. Flash Memory | Integrated Circuit Memory

7. Flash Memory | Integrated Circuit Memory

6. Electrically Erasable Programmable ROM (EEPROM) | Integrated Circuit Memories

6. Electrically Erasable Programmable ROM (EEPROM) | Integrated Circuit Memories

5. Erasable Programmable ROM (EPROM) | Integrated Circuit Memories

5. Erasable Programmable ROM (EPROM) | Integrated Circuit Memories

4. Read Only Memory (ROM) | Integrated Circuit Memories

4. Read Only Memory (ROM) | Integrated Circuit Memories

3. Classification of Memories | Integrated Circuit Memories

3. Classification of Memories | Integrated Circuit Memories

2. Memory basics | Integrated Circuit Memories

2. Memory basics | Integrated Circuit Memories

1. Introduction to Integrated Circuit Memories

1. Introduction to Integrated Circuit Memories

Clock Reconvergence Pessimism Removal (CRPR) | STA

Clock Reconvergence Pessimism Removal (CRPR) | STA

Pins, ports and interfaces | VLSI design

Pins, ports and interfaces | VLSI design

Parasitic Extraction and Back Annotation | VLSI Physical Design

Parasitic Extraction and Back Annotation | VLSI Physical Design

Concept of Mutex | Software and physical design (IR drop) perspective

Concept of Mutex | Software and physical design (IR drop) perspective

Timing path | Slack or Margin and other terminologies

Timing path | Slack or Margin and other terminologies

Timing Arc in STA | Delay calculation

Timing Arc in STA | Delay calculation

STA in ASIC design flow | Accuracy of STA

STA in ASIC design flow | Accuracy of STA

Basic terminologies in STA | Static timing analysis

Basic terminologies in STA | Static timing analysis

Difference between STA and Dynamic timing analysis | STA vs DTA

Difference between STA and Dynamic timing analysis | STA vs DTA

Introduction to Static Timing Analysis | STA , Physical Design, Synthesis in VLSI

Introduction to Static Timing Analysis | STA , Physical Design, Synthesis in VLSI

What is overlay in Integrated Circuits ? | DFM

What is overlay in Integrated Circuits ? | DFM

Design for Manufacturability (DFM ) | DRCs, Dummyfill

Design for Manufacturability (DFM ) | DRCs, Dummyfill

Physical Design Flow | VLSI back end | IC Design

Physical Design Flow | VLSI back end | IC Design

Emulation in VLSI | Functional Verification, Simulation, Formal Verification

Emulation in VLSI | Functional Verification, Simulation, Formal Verification

Inputs to VLSI Physical Design | LEF, DEF, LIB, TLUP, netlist, SDC files

Inputs to VLSI Physical Design | LEF, DEF, LIB, TLUP, netlist, SDC files

VLSI ASIC Design flow

VLSI ASIC Design flow

Hierarchy, Regularity, Modularity and Locality | Structured Design Strategies in VLSI

Hierarchy, Regularity, Modularity and Locality | Structured Design Strategies in VLSI

Design for Testability | An introduction to DFT

Design for Testability | An introduction to DFT

Virtual Clock | Static Timing Analysis

Virtual Clock | Static Timing Analysis

Strained Silicon - Part 2: Mobility Enhancement

Strained Silicon - Part 2: Mobility Enhancement

Strained Silicon - Part 1: Understanding mobility

Strained Silicon - Part 1: Understanding mobility

High-K and Low-K dielectrics in VLSI | IC manufacturing

High-K and Low-K dielectrics in VLSI | IC manufacturing

Transition Frequency of MOS transistor and it's significance in VLSI

Transition Frequency of MOS transistor and it's significance in VLSI

Libraries and Intellectual Properties in VLSI

Libraries and Intellectual Properties in VLSI

Combinational Logic Hazards | Hazard free digital circuits

Combinational Logic Hazards | Hazard free digital circuits

Sequential Circuit Models | Mealy and Moore Machine Models

Sequential Circuit Models | Mealy and Moore Machine Models

What are SOCs and ASICs? | Difference between SOCs and ASICs

What are SOCs and ASICs? | Difference between SOCs and ASICs

Metal Layer basics in VLSI

Metal Layer basics in VLSI

Clock Skew and Clock Jitter

Clock Skew and Clock Jitter

Antenna Effect in VLSI | How to fix antenna violations?

Antenna Effect in VLSI | How to fix antenna violations?

Power Integrity and IR drop | Techniques to reduce IR drop

Power Integrity and IR drop | Techniques to reduce IR drop

Power Gating and Mother/Daughter cells in VLSI

Power Gating and Mother/Daughter cells in VLSI

Signal Integrity Issues in VLSI | Crosstalk, Glitch | How to avoid these issues?

Signal Integrity Issues in VLSI | Crosstalk, Glitch | How to avoid these issues?

Setup time, Hold time and Metastability | What's the origin? Can these be negative?

Setup time, Hold time and Metastability | What's the origin? Can these be negative?

Electromigration and Reliability in VLSI | Why do chips die?

Electromigration and Reliability in VLSI | Why do chips die?

Buffer and Inverter insertion in Timing paths | Inverters vs Buffers | Buffer as a repeater

Buffer and Inverter insertion in Timing paths | Inverters vs Buffers | Buffer as a repeater

Timing Classification of Digital Systems | Synchronous, Asynchronous, Mesochronous ....

Timing Classification of Digital Systems | Synchronous, Asynchronous, Mesochronous ....

Understanding CMOS inverter | Why NMOS passes strong 0 and PMOS passes strong 1

Understanding CMOS inverter | Why NMOS passes strong 0 and PMOS passes strong 1

Clock Gating | Integrated Clock Gating cell

Clock Gating | Integrated Clock Gating cell

Middle End of the Line in CMOS fabrication process | Contact & Metal Layer M0

Middle End of the Line in CMOS fabrication process | Contact & Metal Layer M0

Why do we use polysilicon gate in VLSI?

Why do we use polysilicon gate in VLSI?

Why do we use multiple active contacts ?

Why do we use multiple active contacts ?

Latch-Up phenomenon in CMOS circuits and Prevention Techniques

Latch-Up phenomenon in CMOS circuits and Prevention Techniques

Automating calculations using .meas in LTspice | Measuring in LT spice

Automating calculations using .meas in LTspice | Measuring in LT spice

Differential Amplifier with Active Load in LTspice

Differential Amplifier with Active Load in LTspice

4. CS amplifier with current mirror load in LTspice

4. CS amplifier with current mirror load in LTspice

3. CS Amplifier with Diode Connected Load in LTspice

3. CS Amplifier with Diode Connected Load in LTspice

2. CS amplifier with Current Source Load in LTspice

2. CS amplifier with Current Source Load in LTspice

1. CS Amplifier with Resistor Load in LTspice | Analog Electronics | Simulation

1. CS Amplifier with Resistor Load in LTspice | Analog Electronics | Simulation

Full Bridge Rectifier using MOSFETs in LTspice

Full Bridge Rectifier using MOSFETs in LTspice

CMOS Inverter Midpoint voltage - DC analysis | Including Libray | Using Parameters in LT spice

CMOS Inverter Midpoint voltage - DC analysis | Including Libray | Using Parameters in LT spice

Full Bridge inverter in LT spice

Full Bridge inverter in LT spice

Half bridge inverter in LT Spice

Half bridge inverter in LT Spice

Inverting Amplifier using LM 741 Op-amp in LT spice

Inverting Amplifier using LM 741 Op-amp in LT spice

PMOS V-I characteristics using LT spice

PMOS V-I characteristics using LT spice

NMOS output characteristics in LTspice | LT spice simulation

NMOS output characteristics in LTspice | LT spice simulation

NMOS input characteristics in LT Spice

NMOS input characteristics in LT Spice

Customising LT spice | how to change background and colors in LT spice

Customising LT spice | how to change background and colors in LT spice

Recording and playing audio using Matlab

Recording and playing audio using Matlab

Designing helical antenna in Matlab part 2 | Impedance, Reflection co-efficient, Return Loss, VSWR

Designing helical antenna in Matlab part 2 | Impedance, Reflection co-efficient, Return Loss, VSWR

Delta modulation using MATLAB Simulink | Digital Communication project

Delta modulation using MATLAB Simulink | Digital Communication project

Designing Helical Antenna using Matlab part 1

Designing Helical Antenna using Matlab part 1

Addition of ODD bytes 8086 microprocessor programming

Addition of ODD bytes 8086 microprocessor programming

Interrupt INT 21H in 8086 microprocessor

Interrupt INT 21H in 8086 microprocessor

Convert BCD to hexadecimal in 8086 microprocessor programming

Convert BCD to hexadecimal in 8086 microprocessor programming

Conversion of Hexadecimal to BCD number | 8086 microprocessor programming

Conversion of Hexadecimal to BCD number | 8086 microprocessor programming

Basics of 8086 microprocessors programming | String palindrome assembly level code

Basics of 8086 microprocessors programming | String palindrome assembly level code