XiangShan: an Open-source High-performance RISC-V Processor - Yungang Bao, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)

XiangShan, released jointly by Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS) and Peng Cheng Laboratory (PCL), is an open-source high-performance RISC-V processor started in June 2020. It's written in Chisel hardware construction language and supports RV64GC instruction set. During the development of XiangShan, they built many open-source agile tools to speed up the development, including differential testing, simulation snapshot, RISC-V checkpoints, etc. XiangShan has been taped-out for the first time in July 2021 and is expected to have its second generation taped-out at early 2022. XiangShan has been open-sourced at GitHub and contributions are welcome. In this talk, Dr. Bao will focus on the experience in chip agile development and introduce the development tools used in the XiangShan project

For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: [ Ссылка ]

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