At reset why all parallel ports are configured as an input port is described in detail through datasheet analysis of block diagram, program memory, data memory and internal structure of parallel ports.
PORT LATCH, FET DRIVER, PORT PINS, PULL-UP RESISTORS, TRI-STATE BUFFERS IN PORTS are also discussed.
All four parallel port internal structures are clearly simulated and demonstrated in KEIL IDE.
![](https://s2.save4k.ru/pic/YAQfnQK8C1Y/mqdefault.jpg)