In this video, I would like to show you how to create a fresh project with Xilinx Vivado 2019.2 version. And then how to create VHDL sources and then finally simulate them with a testbench and verify the results after checking the simulation waveform.

Link to my VHDL Blog with many Examples : [ Ссылка ]
Link to my Verilog Blog with many Examples : [ Ссылка ]

Link to the code which was tested on this Video: [ Ссылка ]

Contact me for VHDL/Verilog Tutoring : [ Ссылка ]

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