Title: 10 kV SiC MOSFET Power Module with Double-Sided Jet-Impingement Cooling
Presenter: Mark Cairnie was selected as the best presenter in Technical Session 2: Characterization and packaging of WBG/UWBG Devices at the 2023 CPES Annual Conference.
Advisor: Christina DiMarino
Abstract: A 10 kV, 50 A SiC MOSFET phase-leg package is proposed which combines an innovative lateral spring-pin terminal with wirebond-less molybdenum interconnects to enable 10 nH parasitic inductance and double-sided cooling. The module utilizes additively-manufactured, direct jet-impingement coolers, integrated into the module housing to cool the four, 3rd generation 10 kV SiC MOSFET dies. When compared to conventional cold plates, the integrated coolers allow for the removal of the baseplate and cold plate fixtures/clamps, while also alleviating certain insulation concerns. A mix of experimental measurements and analytical models were used to verify the thermal performance of the coolers and compare them to commercially available options. According to the experimental results, the integrated coolers in conjunction with the double-sided cooling can dissipate a heat load of 200 W/cm2 with inlet temperature of 45◦C while maintaining a maximum junction temperature 160◦C. The double-sided cooling provided a 30% decrease in effective θjc, from 0.253 K/W to 0.176 K/W per switch position, when compare to the equivalent single-sided cooled package.
Keywords: double-sided cooling, field grading, silicon carbide, high density, packaging
