This is the fourth in a series of videos about latches and flip-flops. These bi-stable combinations of logic gates form the basis of computer memory, counters, shift registers, and more. In particular, this video covers the clocked D latch, that is, a D latch controlled by a computer clock signal which is important for synchronisation. It shows how an edge detection device can be built from a NOT gate and an AND gate in order to isolate the rising edge of the clock cycle. It then shows how this can be used to turn a level triggered D latch into an edge triggered D latch – the so called pulse latch. The asynchronous inputs PRE and CLR in a clocked D latch are also mentioned. The video that follows this one builds upon the principles covered and goes on to describe the master slave D type flip flop.
